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| motorola.com/semiconductors m68hc08 microcontrollers m c 6 8 h c 9 0 8 q f 4 data sheet 6/2004 rev. 1.0 mc68hc908qf4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola 3 mc68hc908qf4 data sheet to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://motorola.com/semiconductors/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . revision history data sheet mc68hc908qf4 ? rev. 1.0 4 revision history motorola revision history date revision level description page number(s) october, 2003 n/a initial release n/a june, 2004 1.0 removed references to mc68hc908qf3, mc68hc908qf2, and mc68HC908QF1 throughout 17.4 thermal characteristics ? updated 32-pin tqfp value 176 18.2 mc order numbers ? updated table entries for mc order numbers 193 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola list of sections 5 data sheet ? mc68hc908qf4 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 section 3. analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . 37 section 4. auto wakeup module (awu) . . . . . . . . . . . . . . . . . . . . . . . . 45 section 5. configuration regi ster (config) . . . . . . . . . . . . . . . . . . . . 51 section 6. computer operat ing properly (cop) . . . . . . . . . . . . . . . . . 55 section 7. central processor un it (cpu) . . . . . . . . . . . . . . . . . . . . . . . 59 section 8. external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 section 9. keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . 79 section 10. low-voltage inhibit (lvi) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 section 11. oscillator module (osc). . . . . . . . . . . . . . . . . . . . . . . . . . . 91 section 12. pll tuned uhf tr ansmitter module. . . . . . . . . . . . . . . . 101 section 13. input/output (i/o) ports . . . . . . . . . . . . . . . . . . . . . . . . . . 111 section 14. system integrat ion module (sim) . . . . . . . . . . . . . . . . . . 119 section 15. timer interface module (tim) . . . . . . . . . . . . . . . . . . . . . . 137 section 16. development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 section 17. electrical specif ications . . . . . . . . . . . . . . . . . . . . . . . . . 175 section 18. ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections data sheet mc68hc908qf4 ? rev. 1.0 6 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola table of contents 7 data sheet ? mc68hc908qf4 table of contents section 1. gener al description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 section 2. memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6 flash memory (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.6.1 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.6.2 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6.3 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6.4 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6.5 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.6 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 section 3. anal og-to-digital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 adc port i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3 conversion time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908qf4 ? rev. 1.0 8 table of contents motorola 3.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.6 input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.7 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.7.2 adc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7.3 adc input clock register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 section 4. auto wakeup module (awu) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.1 port a i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6.2 keyboard status and control register . . . . . . . . . . . . . . . . . . . . . . . 48 4.6.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . 49 section 5. configurat ion register (config) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 section 6. computer o perating properly (cop) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.1 busclkx4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.6 copd (cop disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.7 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908qf4 ? rev. 1.0 data sheet motorola table of contents 9 6.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.7.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.8 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 section 7. central processor un it (cpu) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.3.2 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 section 8. external interrupt (irq) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 section 9. keyboard in terrupt module (kbi) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.3.1 keyboard operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.3.2 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.5 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908qf4 ? rev. 1.0 10 table of contents motorola 9.6 keyboard module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 83 9.7 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.7.1 keyboard status and control register . . . . . . . . . . . . . . . . . . . . . . . 84 9.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . 85 section 10. low-voltage inhibit (lvi) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.3.1 polled lvi operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.3 voltage hysteresis protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.4 lvi status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.6.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 section 11. oscillat or module (osc) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.3.1 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.3.1.1 internal oscillator trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.1.2 internal to external clock switching . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.2 external oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.3 xtal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.4 rc oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.4 oscillator module signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.4.1 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.4.2 crystal amplifier output pin (osc 2/pta4/busclkx4). . . . . . . . . . 96 11.4.3 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . 96 11.4.4 xtal oscillator clock (xtalclk) . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.4.5 rc oscillator clock (rcclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.4.6 internal oscillator clock (intclk) . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.7 oscillator out 2 (busclkx4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.8 oscillator out (busclkx2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908qf4 ? rev. 1.0 data sheet motorola table of contents 11 11.6 oscillator during break mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.7 config2 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.8 input/output (i/o) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.8.1 oscillator status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.8.2 oscillator trim register (osctrim) . . . . . . . . . . . . . . . . . . . . . . . . 99 section 12. p ll tuned uhf tra nsmitter module 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.2 transmitter functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3 phase-lock loop (pll) and local oscillator . . . . . . . . . . . . . . . . . . . . 103 12.4 rf output stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.5 modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.6 microcontroller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.7 state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.8 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.9 data clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.10 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.10.1 application schematics in ook and fsk modulation . . . . . . . . . . 107 12.10.2 complete application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 109 section 13. input/o utput (i/o) ports 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.2.1 port a data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.2.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.2.3 port a input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . 114 13.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.3.1 port b data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.3.3 port b input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . 116 section 14. system in tegration module (sim) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.2 rst and irq pins initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . 121 14.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 14.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 14.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . 122 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908qf4 ? rev. 1.0 12 table of contents motorola 14.4 reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 14.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 14.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . . . . . . . 123 14.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14.4.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . 124 14.4.2.3 illegal opcode reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 14.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . 126 14.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . . . . . . . 126 14.5.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 14.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 14.6.1 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 14.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.6.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 14.6.2 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.6.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.6.2.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.6.2.3 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . 132 14.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 14.7.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 14.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 14.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 14.8.1 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 14.8.2 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 section 15. timer interface module (tim) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 15.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.4.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.4.3.1 unbuffered output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.4.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 15.4.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 15.4.4.1 unbuffered pwm signal generation. . . . . . . . . . . . . . . . . . . . . . 143 15.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . 144 15.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908qf4 ? rev. 1.0 data sheet motorola table of contents 13 15.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 15.6 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 15.7 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.8 input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.8.1 tim clock pin (pta2/tclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.8.2 tim channel i/o pins (pta0/tch0 and pta1/tch1) . . . . . . . . . . 146 15.9 input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 15.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . 147 15.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.9.3 tim counter modulo registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.9.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . 150 15.9.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 section 16. development support 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.2 break module (brk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.2.1.1 flag protection during break interrupt s . . . . . . . . . . . . . . . . . . . 158 16.2.1.2 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16.2.1.3 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16.2.2 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 16.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . 159 16.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 16.2.2.3 break auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 16.2.2.4 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2.2.5 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.3 monitor module (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.3.1.1 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 16.3.1.2 forced monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.3.1.3 monitor vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.3.1.4 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.3.1.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.3.1.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.3.1.7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 16.3.2 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 section 17. electr ical specifications 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.3 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908qf4 ? rev. 1.0 14 table of contents motorola 17.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 17.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 17.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 17.7 typical 3.0-v output drive characteristics. . . . . . . . . . . . . . . . . . . . . . 179 17.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 17.9 supply current characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 17.10 analog-to-digital (adc) converter characte ristics. . . . . . . . . . . . . . . . 183 17.10.1 adc electrical operating conditions . . . . . . . . . . . . . . . . . . . . . . . 183 17.10.2 adc performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 183 17.11 timer interface module characteristics . . . . . . . . . . . . . . . . . . . . . . . . 184 17.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 17.13 uhf transmitter module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 17.13.1 uhf module electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 186 17.13.2 uhf module output power measurement . . . . . . . . . . . . . . . . . . . 190 section 18. ordering information and mechanical specifications 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.3 32-pin plastic low-profile quad flat pack (case no. 873a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola general description 15 data sheet ? mc68hc908qf4 section 1. general description 1.1 introduction the mc68hc908qf4 mcu is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontrolle r units (mcus). optimized for low-power operation and available in a small 32-pin low-profile quad flat pack (lqfp), this mcu is well suited for remote keyles s entry (rke) transmitter designs, tire pressure monitoring (tpm), or other remote sensing and wireless rf data transmission applications. all mcus in the m68hc908 family use the enhanced m68hc08 central processor unit (cpu08) and are available with a va riety of modules, memory sizes and types, and package types. 1.2 features features of the mc68hc908qf4 mcu include: high-performance m68hc08 architecture fully upward-compatible object co de with m6805, m146805, and m68hc05 families operating voltage range of 2.2 to 3.6 v maximum internal bus frequency of 2 mhz trimmable internal oscillator ? 4-mhz operating frequency for a 1-mhz bus frequency ? 8-bit trim capability allows 0.4% accuracy (1) ? 25 percent accuracy untrimmed auto wakeup from stop capability 4096 bytes of on-chip flash memory flash program memory security (2) 128 bytes of on-chip ram 16-bit, 2-channel timer interface module (tim) 4 channel, 8-bit analog-to-digital converter (adc) 1. the oscillator frequency is guaranteed to 5% ov er temperature and voltage range after trimming. 2. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc908qf4 ? rev. 1.0 16 general description motorola 13 general-purpose input/output (i/o) ports: ? six shared with keyboard wakeup function ? three shared with the timer module, irq ? port a pins have 3-ma sink capabilities low-voltage inhibit (lvi) modul e with selectable trip points: ? 2.12 v detection forces mcu into reset ? 2.32 v detection sets indicator flag 6-bit keyboard interrupt with wakeup feature (kbi) external asynchronous interrupt pin with internal pullup (irq ) ultra high frequency (uhf) rf transmitter: ? ultra low sleep mode current ? ask and fsk modulation selectable system protection features: ? computer operating properly (cop) reset ? low-voltage detection with reset ? illegal opcode detection with reset ? illegal address detection with reset 32-pin plastic lqfp package power saving stop and wait modes master reset pin (rst ) shared with general-purpose i/o pin features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c language support 1.3 mcu bl ock diagram figure 1-1 shows the structure of the mc68hc908qf4 mcu. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68hc908qf4 ? rev. 1.0 data sheet motorola general description 17 figure 1-1. block diagram 1.4 pin assignments the mc68hc908qf4 is available in a 32- pin plastic low-prof ile quad flat pack (lqfp). figure 1-2 shows the pin assignment for this package. v cc mode pllen data bs op1 gnd rext xtal1 xtal0 upclk pfd uhf transmitter rst , irq : pins have internal (about 30k ohms) pull up pta[0:5]: high current si nk and source capability pta[0:5]: pins have programmabl e keyboard interrupt and pull up pta0/ad0/tch0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 16-bit timer module cop module monitor rom ptb0 ptb ddrb m68hc08 cpu pta ddra ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb7 8-bit adc 128 bytes ram power supply v dd v ss mc68hc908qf4 4096 bytes user flash f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc908qf4 ? rev. 1.0 18 general description motorola 1.5 pin functions table 1-1 provides a description of the pin functions other than those dedicated to the uhf module which are shown in table 1-2 . figure 1-2. mc68hc908qf4 pin assignments table 1-1. pin functions pin name description input/output v dd power supply power v ss power supply ground power pta0 pta0 ? general purpose i/o port input/output tch0 ? timer channel 0 i/o input/output kbi0 ? keyboard interrupt input 0 input pta1 pta1 ? general purpose i/o port input/output tch1 ? timer channel 1 i/o input/output kbi1 ? keyboard interrupt input 1 input ptb0 v dd v ss ptb1 pta0/tch0/kbi0 data clk data band pta5/osc1/kbi5 ptb6 ptb7 xtal0 xtal1 gnd pta1/tch1/kbi1 ptb2 ptb3 pta2/irq /kbi2 pta3/rst /kbi3 rext cfsk v cc rfout gndrf v cc enable mode 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 1 pta4/osc2/kbi4 ptb4 ptb5 nc nc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions mc68hc908qf4 ? rev. 1.0 data sheet motorola general description 19 pta2 pta2 ? general purpose input-only port input irq ? external interrupt with programmable pullup and schmitt trigger input input kbi2 ? keyboard interrupt input 2 input pta3 pta3 ? general purpose i/o port input/output rst ? reset input, active low with internal pullup and schmitt trigger input kbi3 ? keyboard interrupt input 3 input pta4 pta4 ? general purpose i/o port input/output osc2 ?xtal oscillator output (xtal option only) rc or internal oscillator output (osc2en = 1 in ptapue register) output output kbi4 ? keyboard interrupt input 4 input pta5 pta5 ? general purpose i/o port input/output osc1 ?xtal, rc, or external oscillator input input kbi5 ? keyboard interrupt input 5 input ptb[0:7] 8 general-purpose i/o ports input/output table 1-2. uhf transmitter pins pin function description 6 gnd ground 7 xtal1 reference oscillator input 8 xtal0 reference oscillator output 9 rext output amplifier current setting resistor 10 cfsk fsk switch output 11 v cc power supply 12 rfout power amplifier output 13 gndrf power amplifier ground 14 v cc power supply 15 enable enable input 16 mode modulation type selection input 17 band frequency band selection 18 data data input 19 dataclk clock output to the microcontroller table 1-1. pin fun ctions (continued) pin name description input/output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc908qf4 ? rev. 1.0 20 general description motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola memory 21 data sheet ? mc68hc908qf4 section 2. memory 2.1 introduction the central processor unit (cpu08) can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 4096 bytes of user flash 128 bytes of random access memory (ram) 48 bytes of user-defined vectors, located in flash 416 bytes of monitor read-only memory (rom) 1536 bytes of flash program and erase routines, located in rom 2.2 unimplemented memory locations accessing an unimplemented location can have unpredictable effects on mcu operation. in figure 2-1 and in register figures in this document, unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in figure 2-1 and in register figures in this document, reserved locations are marked with the word reserved or with the letter r. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908qf4 ? rev. 1.0 22 memory motorola $0000 $003f i/o registers 64 bytes $0040 $007f reserved 64 bytes $0080 $00ff ram 128 bytes $0100 $27ff unimplemented 9984 bytes $2800 $2dff auxiliary rom 1536 bytes $2e00 $edff unimplemented 49152 bytes $ee00 $fdff flash memory 4096 bytes $fe00 $fe0f system registers $fe10 $ffaf monitor rom 416 bytes $ffb0 $ffbd flash 14 bytes $ffbe flash block protect register (flbpr) $ffbf reserved flash $ffc0 internal oscillator trim value $ffc1 reserved flash $ffc2 $ffcf flash 14 bytes $ffd0 $ffff user vectors 48 bytes figure 2-1. memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory input/output (i/o) section mc68hc908qf4 ? rev. 1.0 data sheet motorola memory 23 2.4 input/output (i/o) section addresses $0000?$003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: $fe00 ? break status register, bsr $fe01 ? reset status register, srsr $fe02 ? break auxiliary register, brkar $fe03 ? break flag control register, bfcr $fe04 ? interrupt status register 1, int1 $fe05 ? interrupt status register 2, int2 $fe06 ? interrupt status register 3, int3 $fe07 ? reserved $fe08 ? flash control register, flcr $fe09 ? break address register high, brkh $fe0a ? break address register low, brkl $fe0b ? break status and control register, brkscr $fe0c ? lvi status register, lvisr $fe0d ? reserved $ffbe ? flash block protect register, flbpr $ffc0 ? internal osc trim value ? optional $ffff ? cop control register, copctl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908qf4 ? rev. 1.0 24 memory motorola addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 112. read: r awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 115. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 $0003 unimplemented $0004 data direction register a (ddra) see page 113. read: r r ddra5 ddra4 ddra3 0 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 115. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 $000a unimplemented $000b port a input pullup enable register (ptapue) see page 114. read: osc2en 0 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000c port b input pullup enable register (ptbpue) see page 116. read: ptbpue7 ptbpue6 ptbpue5 ptbpue4 ptbpue3 ptbpue2 ptbpue1 ptbpue0 write: reset:00000000 $000d $0019 unimplemented $001a keyboard status and control register (kbscr) see page 84. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) see page 85. read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c unimplemented = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 1 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory input/output (i/o) section mc68hc908qf4 ? rev. 1.0 data sheet motorola memory 25 $001d irq status and control register (intscr) see page 77. read:0000irqf10 imask1 mode1 write: ack1 reset:00000000 $001e configuration register 2 (config2) (1) see page 51. read: irqpud irqen r oscopt1 oscopt0 r r rsten write: reset:00000000 (2) 1. one-time writable register after each reset. 2. rsten reset to 0 by a power-on reset (por) only. $001f configuration register 1 (config1) (1) see page 52. read: coprs lvistop lvirstd lvipwrd lvdlvr ssrec stop copd write: reset:00000 (2) 000 1. one-time writable register after each reset. exceptions are lvdlvr and lvirstd bits. 2. lvdlvr reset to 0 by a power-on reset (por) only. $0020 tim status and control register (tsc) see page 147. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim counter register high (tcnth) see page 149. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0022 tim counter register low (tcntl) see page 149. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) see page 149. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $0024 tim counter modulo register low (tmodl) see page 149. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $0025 tim channel 0 status and control register (tsc0) see page 150. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim channel 0 register high (tch0h) see page 153. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 2 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908qf4 ? rev. 1.0 26 memory motorola $0027 tim channel 0 register low (tch0l) see page 153. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset $0028 tim channel 1 status and control register (tsc1) see page 150. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim channel 1 register high (tch1h) see page 153. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $002a tim channel 1 register low (tch1l) see page 153. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset $002b $0035 unimplemented $0036 oscillator status register (oscstat) see page 98. read: rrrrrrecgon ecgst write: reset:00000000 $0037 unimplemented read: $0038 oscillator trim register (osctrim) see page 99. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $0039 $003f unimplemented $fe00 break status register (bsr) see page 161. read: rrrrrr sbsw r write: see note 1 reset: 0 1. writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 135. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 3 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory input/output (i/o) section mc68hc908qf4 ? rev. 1.0 data sheet motorola memory 27 $fe02 break auxiliary register (brkar) see page 160. read:0000000 bdcop write: reset:00000000 $fe03 break flag control register (bfcr) see page 161. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 77. read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 77. read:if140000000 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 77. read:0000000if15 write:rrrrrrrr reset:00000000 $fe07 reserved rrrrrrrr $fe08 flash control register (flcr) see page 30. read:0000 hven mass erase pgm write: reset:00000000 $fe09 break address high register (brkh) see page 160. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $fe0a break address low register (brkl) see page 160. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 159. read: brke brka 000000 write: reset:00000000 $fe0c lvi status register (lvisr) see page 89. read:lviout000000r write: reset:00000000 $fe0d $fe0f reserved for flash test rrrrrrrr addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 4 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908qf4 ? rev. 1.0 28 memory motorola $ffb0 $ffbd unimplemented $ffbe flash block protect register (flbpr) see page 35. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 $ffbf unimplemented $ffc0 internal oscillator trim value (optional) read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $ffc1 reserved rrrrrrrr $ffc2 $ffcf unimplemented $ffff cop control register (copctl) see page 57. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 5 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory random-access memory (ram) mc68hc908qf4 ? rev. 1.0 data sheet motorola memory 29 table 2-1 shows the mc68hc908qf4 reset and interrupt vectors. . 2.5 random-access memory (ram) addresses $0080?$00ff are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer al lows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. before processing an interrupt, the central pr ocessor unit (cpu) uses five bytes of the stack to save the contents of the cpu registers. note: for m6805, m146805, and m68hc05 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines . the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. table 2-1. vector addresses vector priority vector address vector lowest highest if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 if6 ? not used if5 $fff2 tim overflow vector (high) $fff3 tim overflow vector (low) if4 $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) if3 $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) if2 ? not used if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) $ffff reset vector (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908qf4 ? rev. 1.0 30 memory motorola 2.6 flash memory (flash) this subsection describes the operat ion of the embedded flash memory. the flash memory can be read, programmed, and erased from a single external supply. the program and erase operat ions are enabled through the use of an internal charge pump. the flash memory consists of an array of 4096 bytes with an additional 48 bytes for user vectors. the minimum size of flash memory that can be erased is 64 bytes; and the maximum size of flash memory that can be programmed in a program cycle is 32 bytes (a row). program and erase operations are facilitated through control bits in the flash control register (flcr). details for these operations appear later in this section. the address ranges for the user memory and vectors are: $ee00 ? $fdff; user memory, 4096 bytes $ffd0 ? $ffff; user interrupt vectors, 48 bytes. note: an erased bit reads as 1 and a programmed bit reads as 0. a security feature prevents viewing of the flash contents. (1) 2.6.1 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high voltage enable bit this read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. it can only be set if either pgm =1 or erase =1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit configures the memory for mass erase operation. 1 = mass erase operation selected 0 = mass erase operation unselected 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-3. flash control register (flcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory flash memory (flash) mc68hc908qf4 ? rev. 1.0 data sheet motorola memory 31 erase ? erase control bit this read/write bit configures the memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for program operation. pgm is interlocked with the erase bit such that bot h bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 2.6.2 flash page erase operation use the following procedure to erase a page of flash memory. a page consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80, or $xxc0. the 48-byte user interrupt vectors area also forms a page. any flash memory page can be erased alone. 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 1 ms or 4 ms). 7. clear the erase bit. 8. wait for a time, t nvh (minimum 5 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locati ons cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. in applications that need up to 10,000 program/erase cycles, use the 4 ms page erase specification to get improved long -term reliability. any application can use this 4 ms page erase specification. ho wever, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specif ication to get a lower minimum erase time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908qf4 ? rev. 1.0 32 memory motorola 2.6.3 flash mass erase operation use the following procedure to erase the entire flash memory to read as 1: 1. set both the erase bit and the mass bit in the flash control register. 2. read from the flash block protect register. 3. write any data to any flash address (1) within the flash memory address range. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 4 ms). 7. clear the erase and mass bits. note: mass erase is disabled whene ver any block is protected (flbpr does not equal $ff). 8. wait for a time, t nvh1 (minimum 100 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locati ons cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.6.4 flash program operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addresses $xx00, $xx20, $xx40, $xx60, $xx80, $xxa0, $xxc0, or $xxe0. use the followi ng step-by-step procedure to program a row of flash memory figure 2-4 shows a flowchart of the programming algorithm. note: only bytes which are currently $ff may be programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read from the flash block protect register. 3. write any data to any flash location within the address range desired. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t pgs (minimum 5 s). 1. when in monitor mode, with security sequence failed (see 16.3.2 security ), write to the flash block protect register instead of any flash address. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory flash memory (flash) mc68hc908qf4 ? rev. 1.0 data sheet motorola memory 33 7. write data to the flash address being programmed (1) . 8. wait for time, t prog (minimum 30 s). 9. repeat step 7 and 8 until all desired bytes within the row are programmed. 10. clear the pgm bit (1) . 11. wait for time, t nvh (minimum 5 s). 12. clear the hven bit. 13. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: the cop register at location $ffff sh ould not be written between steps 5-12, when the hven bit is set. since this regi ster is located at a valid flash address, unpredictable behavior may occur if this location is written while hven is set. this program sequence is repeated throughout the memory until all data is programmed. note: programming and erasing of flash locati ons cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum, see 17.12 memory characteristics . 2.6.5 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provisi on is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash blo ck protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a lo cation defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note: in performing a program or erase operation, the flash block protect register must be read after setting the pgm or erase bit and before asserting the hven bit. when the flbpr is programmed with all 0 s, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. 1. the time between each flash address change, or the time between the last flash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog maximum. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908qf4 ? rev. 1.0 34 memory motorola figure 2-4. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming 1 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (32 bytes) of flash memory 9 read the flash block protect register 2 notes: the time between each flash address change (step 6 to step 9), or the time between the last flash addres s programmed to clearing pgm bit (step 6 to step 9) must not exceed the maximum programming time, t prog , maximum. this row program algorithm assumes the row/s to be programmed are initially erased. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory flash memory (flash) mc68hc908qf4 ? rev. 1.0 data sheet motorola memory 35 when bits within the flbpr are programmed, they lock a block of memory. the address ranges are shown in 2.6.6 flash block protect register . once the flbpr is programmed with a value other than $ff, any erase or program of the flbpr or the protected block of flash memory is prohibited. mass erase is disabled whenever any block is protec ted (flbpr does not equal $ff). the flbpr itself can be erased or program med only with an external voltage, v tst , present on the irq pin. this voltage also allows entry from reset into the monitor mode. 2.6.6 flash block protect register the flash block protect register is implemented as a byte within the flash memory, and therefore can only be written during a programming sequence of the flash memory. the value in this register determines the starting address of the protected range within the flash memory. bpr[7:0] ? flash protection register bits [7:0] these eight bits in flbpr represent bits [13:6] of a 16-bit memory address. bits [15:14] are 1s and bits [5:0] are 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this start address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be xx00, xx40, xx80, or xxc0 within the flash memory. see figure 2-6 and table 2-2 . figure 2-6. flash block protect start address address: $ffbe bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:uuuuuuuu u = unaffected by reset. initial value from factory is 1. write to this register is by a programming sequence to the flash memory. figure 2-5. flash block protect register (flbpr) 0 0 0 0 0 1 1 flbpr value start address of 16-bit memory address flash block protect 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908qf4 ? rev. 1.0 36 memory motorola 2.6.7 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the wait instruction should not be execut ed while performing a program or erase operation on the flash, or the operation will discontinue and the flash will be on standby mode. 2.6.8 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash, or the operation will discontinue and the flash will be on standby mode note: standby mode is the power-saving mode of the flash module in which all internal control signals to the flash are inacti ve and the current consumption of the flash is at a minimum. table 2-2. examples of protect start address bpr[7:0] start of address of protect range $00?$b8 the entire flash memory is protected. $b9 ( 1011 1001 )$ee40 (11 10 1110 01 00 0000) $ba ( 1011 1010 )$ee80 (11 10 1110 10 00 0000) $bb ( 1011 1011 ) $eec0 (11 10 1110 11 00 0000) $bc ( 1011 1100 )$ef00 (11 10 1111 00 00 0000) and so on... $de ( 1101 1110 ) $f780 (11 11 0111 10 00 0000) $df ( 1101 1111 )$f7c0 (11 11 0111 11 00 0000) $fe ( 1111 1110 ) $ff80 (11 11 1111 10 00 0000) flbpr, osctrim, and vectors are protected $ff the entire flash memory is not protected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola analog-to-digital converter (adc) 37 data sheet ? mc68hc908qf4 section 3. analog-to-digital converter (adc) 3.1 introduction this section describes the analog-to-digi tal converter (adc). the adc is an 8-bit, 4-channel analog-to-digital converter. 3.2 features features of the adc module include: 4 channels with multiplexed input linear successive approximation with monotonicity 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock frequency figure 3-1 provides a summary of the input/output (i/o) registers. addr.register name bit 7654321bit 0 $003c adc status and control register (adscr) see page 42. read: coco aien adco ch4 ch3 ch2 ch1 ch0 write: reset:00011111 $003d unimplemented $003e adc data register (adr) see page 43. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset $003f adc input clock register (adiclk) see page 44. read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 3-1. adc i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68hc908qf4 ? rev. 1.0 38 analog-to-digital converter (adc) motorola figure 3-2. block diagram highlighting adc block and pins v cc mode pllen data bs op1 gnd rext xtal1 xtal0 upclk pfd uhf transmitter rst , irq : pins have internal (about 30k ohms) pull up pta[0:5]: high current si nk and source capability pta[0:5]: pins have programmabl e keyboard interrupt and pull up pta0/ad0/tch0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 16-bit timer module cop module monitor rom ptb0 ptb ddrb m68hc08 cpu pta ddra ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb7 8-bit adc 128 bytes ram power supply v dd v ss mc68hc908qf4 4096 bytes user flash f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description mc68hc908qf4 ? rev. 1.0 data sheet motorola analog-to-digital converter (adc) 39 3.3 functional description four adc channels are available for sampling external sources at pins pta0, pta1, pta4, and pta5. an analog multiplexer allows the single adc converter to select one of the four adc channels as an adc voltage input (adcvin). adcvin is converted by the successive approxi mation register-based counters. the adc resolution is eight bits. when the conversion is completed, adc puts the result in the adc data register and sets a flag or generates an interrupt. figure 3-3 shows a block diagram of the adc. figure 3-3. adc block diagram internal data bus interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock bus clock ch[4:0] adc data register adiv[2:0] aien coco disable disable adc channel x read ddra write ddra reset write pta read pta ddrax ptax (1 of 4 channels) adcx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68hc908qf4 ? rev. 1.0 40 analog-to-digital converter (adc) motorola 3.3.1 adc port i/o pins pta0, pta1, pta4, and pta5 are general-p urpose i/o pins that are shared with the adc channels. the channel select bits (adc status and control register (adscr), $003c), define which adc channe l/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. writes to the port register or data direction register (ddr) will not have any affect on the port pi n that is selected by the adc. read of a port pin which is in use by the adc will return a 0 if the corresponding ddr bit is at 0. if the ddr bit is 1, the value in the port data latch is read. 3.3.2 voltage conversion when the input voltage to the adc equals v dd , the adc converts the signal to $ff (full scale). if the input voltage equals v ss, the adc converts it to $00. input voltages between v dd and v ss are a straight-line linear conversion. all other input voltages will result in $ff if greater than v dd and $00 if less than v ss . note: input voltage should not exceed the analog supply voltages. 3.3.3 conversion time sixteen adc internal clocks are requir ed to perform one conversion. the adc starts a conversion on the first rising edge of the adc internal clock immediately following a write to the adscr. if the ad c internal clock is selected to run at 1 mhz, then one conversion will take 16 s to complete. with a 1-mhz adc internal clock the maximum sample rate is 62.5 khz. 3.3.4 continuous conversion in the continuous conversion mode (adco = 1), the adc continuously converts the selected channel filling the adc data register (adr) with new data after each conversion. data from the previous conv ersion will be overwritten whether that data has been read or not. conversions wi ll continue until the adco bit is cleared. the coco bit (adscr, $003c) is set after each conversion and will stay set until the next read of the adc data register. when a conversion is in process and the adsc r is written, the current conversion data should be discarded to prevent an incorrect reading. 3.3.5 accuracy and precision the conversion process is monotonic and has no missing codes. 16 adc clock cycles conversion time = adc clock frequency number of bus cycles = conversion time bus frequency f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) interrupts mc68hc908qf4 ? rev. 1.0 data sheet motorola analog-to-digital converter (adc) 41 3.4 interrupts when the aien bit is set, the adc module is capable of generating a central processor unit (cpu) interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at 0. t he coco bit is not used as a conversion complete flag when interrupts are enabled. 3.5 low-power modes the following subsections describ e the adc in low-power modes. 3.5.1 wait mode the adc continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the microcontroller unit (mcu) out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting the ch[4:0] bits in adscr to 1s before executing the wait instruction. 3.5.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode. allow one conversion cycle to stabilize the analog circuitry before using adc data after exiting stop mode. 3.6 input/output signals the adc module has four channels that are shared with i/o port a. adc voltage in (adcvin) is the input voltage signal from one of the four adc channels to the adc module. 3.7 input/output registers these i/o registers control and monitor adc operation: adc status and control register (adscr) adc data register (adr) adc clock register (adiclk) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68hc908qf4 ? rev. 1.0 42 analog-to-digital converter (adc) motorola 3.7.1 adc status and control register the following paragraphs describe the function of the adc status and control register (adscr). when a conversion is in process and the adscr is written, the current conversion data should be disca rded to prevent an incorrect reading. coco ? conversions complete bit in non-interrupt mode (aien = 0), coco is a read-only bit that is set at the end of each conversion. coco will stay set until cleared by a read of the adc data register. reset clears this bit. in interrupt mode (aien = 1), coco is a read-only bit that is not set at the end of a conversion. it always reads as a 0. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or cpu interrupt enabled (aien = 1) note: the write function of the coco bit is reserved. when writing to the adscr register, always have a 0 in the coco bit position. aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when adr is read or adscr is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update adr at the end of each conversion. only one conversion is allowed wh en this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion ch[4:0] ? adc channel select bits ch4, ch3, ch2, ch1, and ch0 form a 5-bit field which is used to select one of the four adc channels. the five select bits are detailed in table 3-1 . care address: $003c bit 7654321bit 0 read: coco aien adco ch4 ch3 ch2 ch1 ch0 write: reset:00011111 = unimplemented figure 3-4. adc status and control register (adscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) input/output registers mc68hc908qf4 ? rev. 1.0 data sheet motorola analog-to-digital converter (adc) 43 should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when the adc is not used. reset sets all of these bits to a 1. note: recovery from the disabled state requires one conversion cycle to stabilize. 3.7.2 adc data register one 8-bit result register is provided. this register is updated each time an adc conversion completes. table 3-1. mux channel select ch4 ch3 ch2 ch1 ch0 adc channel input select 00000 ad0 pta0 00001 ad1 pta1 00010 ad2 pta4 00011 ad3 pta5 00100 ? unused (1) 1. if any unused channels are selected, the resulting adc conversion will be unknown. ? 11010 ? 11011 ? reserved 11 1 0 0 ? unused 11 1 0 1? v dda (2) 2. the voltage levels supplied from inter nal reference nodes, as specified in the table, are used to verify the operatio n of the adc converter both in produc- tion test and for user applications. 11 1 1 0? v ssa (2) 11 1 1 1? adc power off address: $003e bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 3-5. adc data register (adr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68hc908qf4 ? rev. 1.0 44 analog-to-digital converter (adc) motorola 3.7.3 adc input clock register this register selects the clock frequency for the adc. adiv2?adiv0 ? adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit fi eld which selects the divide ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock configurations. the adc clock should be set according to the mcu operating voltage. lower operating voltages will require lower adc clock frequencies for best accuracy. the analog input level should remain stable for the entire conversion time (maximum = 17 adc clock cycles). address: $003f bit 7654321bit 0 read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 3-6. adc input clock register (adiclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 bus clock 1 0 0 1 bus clock 2 0 1 0 bus clock 4 0 1 1 bus clock 8 1 x x bus clock 16 x = don?t care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola auto wakeup module (awu) 45 data sheet ? mc68hc908qf4 section 4. auto wakeup module (awu) 4.1 introduction this section describes the auto wak eup module (awu). the awu generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. figure 4-2 is a block diagram of the awu. 4.2 features features of the auto wakeup module include: one internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector and keyboard interrupt mask bit exit from low-power stop mode without external signals selectable timeout periods dedicated low power internal oscillator separate from the main system clock sources figure 4-1 provides a summary of the input/output (i/o) registers used in conjuction with the awu. addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 48. read: 0 awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $001a keyboard status and control register (kbscr) see page 48. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) see page 49. read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 4-1. awu register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . auto wakeup module (awu) data sheet mc68hc908qf4 ? rev. 1.0 46 auto wakeup module (awu) motorola 4.3 functional description the function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (mcu) ou t of stop mode. the wakeup requests are treated as regular keyboard interrupt requests, with the difference that instead of a pin, the interrupt signal is generated by an internal logic. writing the awuie bit in the keyboard interrupt enable register enables or disables the auto wakeup interrupt input (see figure 4-2 ). a logic 1 applied to the awuireq input with auto wakeup interrupt request enabled, latches an auto wakeup interrupt request. auto wakeup latch, awul, can be read directly from the bit 6 position of port a data register (pta). this is a read-only bit wh ich is occupying an empty bit position on pta. no pta associated registers, such as pta6 data direction or pta6 pullup exist for this bit. entering stop mode will enable the auto wak eup generation logic. an internal rc oscillator (exclusive for the auto wake up feature) drives the wakeup request generator. once the overflow count is reached in the generator counter, a wakeup request, awuireq, is latched and sent to the kbi logic. see figure 4-1 . wakeup interrupt requests will only be serviced if the associated interrupt enable bit, awuie, in kbier is set. the awu shares the keyboard interrupt vector. figure 4-2. auto wakeup interrupt request generation logic d r v dd int rc osc en 32 khz clk rst overflow autowugen short coprs (from config1) 1 = div 2 9 0 = div 2 14 e reset ackk clear rst reset clk (cgmxclk) busclkx4 istop awuireq clrlogic reset awul to pta read, bit 6 q awuie to kbi interrupt logic (see figure 9-3. keyboard interrupt block diagram ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . auto wakeup module (awu) wait mode mc68hc908qf4 ? rev. 1.0 data sheet motorola auto wakeup module (awu) 47 the overflow count can be selected from two options defined by the coprs bit in config1. this bit was ?borrowed? from the computer operating properly (cop) using the fact that the cop feature is idle (no mcu clock available) in stop mode. the typical values of the periodic wakeup request are (at room temperature): coprs = 0: 875 ms @ 3.0 v, 1.1 s @ 2.3 v coprs = 1: 22 ms @ 3.0 v, 27 ms @ 2.3 v the auto wakeup rc oscillator is hi ghly dependent on operating voltage and temperature. this feature is not recommended for use as a time-keeping function. the wakeup request is latched to allow the interrupt source identification. the latched value, awul, can be read directly from the bit 6 position of pta data register. this is a read-only bit which is occupying an empty bit position on pta. no pta associated registers, such as pta6 data, pta6 direction, and pta6 pullup exist for this bit. the latch can be cleared by writing to the ackk bit in the kbscr register. reset also clears the latch. awuie bit in kbi interrupt enable register (see figure 4-2 ) has no effect on awul reading. the awu oscillator and counters are i nactive in normal operating mode and become active only upon entering stop mode. 4.4 wait mode the awu module remains inactive in wait mode. 4.5 stop mode when the awu module is enabled (awuie = 1 in the keyboard interrupt enable register) it is activated automatically upon entering stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. the awu counters start from ?0? each time stop mode is entered. 4.6 input/output registers the awu shares registers with the keyboard interrupt (kbi) module and the port a i/o module. the following i/o registers control and monitor operation of the awu: port a data register (pta) keyboard interrupt status and control register (kbscr) keyboard interrupt enable register (kbier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . auto wakeup module (awu) data sheet mc68hc908qf4 ? rev. 1.0 48 auto wakeup module (awu) motorola 4.6.1 port a i/o register the port a data register (pta) contains a data latch for the state of the awu interrupt request, in addition to the data latches for port a. awul ? auto wakeup latch this is a read-only bit which has the value of the auto wakeup interrupt request latch. the wakeup request signal is generated internally. there is no pta6 port or any of the associated bits such as pta6 data direction or pullup bits. 1 = auto wakeup interrupt request is pending 0 = auto wakeup interrupt request is not pending note: pta5?pta0 bits are not used in conjucti on with the auto wakeup feature. to see a description of these bits, see 13.2.1 port a data register . 4.6.2 keyboard status and control register the keyboard status and control register (kbscr): flags keyboard/auto wakeup interrupt requests acknowledges keyboard/auto wakeup interrupt requests masks keyboard/auto wakeup interrupt requests bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port a or auto wakeup. reset clears the keyf bit. 1 = keyboard/auto wakeup interrupt pending 0 = no keyboard/auto wakeup interrupt pending address: $0000 bit 7654321bit 0 read: 0 awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: 0 0 unaffected by reset = unimplemented figure 4-3. port a data register (pta) address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 4-4. keyboard status and control register (kbscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . auto wakeup module (awu) input/output registers mc68hc908qf4 ? rev. 1.0 data sheet motorola auto wakeup module (awu) 49 ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port a and auto wakeup logic. ackk always reads as 0. reset clears ackk. imaskk? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port a or auto wakeup. reset clears the imaskk bit. 1 = keyboard/auto wakeup interrupt requests masked 0 = keyboard/auto wakeup interrupt requests not masked note: modek is not used in conjuction with the auto wakeup feature. to see a description of this bit, see 9.7.1 keyboard status and control register . 4.6.3 keyboard interrupt enable register the keyboard interrupt enable register (kbier) enables or disables the auto wakeup to operate as a keyboard/auto wakeup interrupt input. awuie ? auto wakeup interrupt enable bit this read/write bit enables the auto wakeup interrupt input to latch interrupt requests. reset clears awuie. 1 = auto wakeup enabled as interrupt input 0 = auto wakeup not enabled as interrupt input note: kbie5?kbie0 bits are not used in conjucti on with the auto wakeup feature. to see a description of these bits, see 9.7.2 keyboard interrupt enable register . address: $001b bit 7654321bit 0 read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 4-5. keyboard interrupt enable register (kbier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . auto wakeup module (awu) data sheet mc68hc908qf4 ? rev. 1.0 50 auto wakeup module (awu) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola configuration register (config) 51 data sheet ? mc68hc908qf4 section 5. configurat ion register (config) 5.1 introduction this section describes the configurati on registers (config1 and config2). the configuration registers enable or disable the following options: stop mode recovery time (32 busclkx4 cycles or 4096 busclkx4 cycles) stop instruction computer operating properly module (cop) cop reset period (coprs): (2 13 ?2 4 ) busclkx4 or (2 18 ?2 4 ) busclkx4 low-voltage inhibit (lvi) enable and trip voltage selection osc option selection irq pin rst pin auto wakeup timeout period 5.2 functional description the configuration registers are used in the initialization of various options. the configuration registers can be written once after each reset. exceptions are bits lvdlvr and lvirstd which may be written at any time. most of the configuration register bits are cleared during reset. since the various options affect the operation of the microcontroller unit (mcu) it is recommended that this register be written immediately after reset. the configuration registers are located at $001e and $001f, and may be read at anytime. address: $001e bit 7654 321bit 0 read: irqpud irqen r oscopt1 oscopt0 r r rsten write: reset:000 0 0 00u por:000 0 0 000 r = reserved u = unaffected figure 5-1. configuration register 2 (config2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) data sheet mc68hc908qf4 ? rev. 1.0 52 configuration register (config) motorola irqpud ? irq pin pullup control bit 1 = internal pullup is disconnected 0 = internal pullup is connected between irq pin and v dd irqen ? irq pin function selection bit 1 = interrupt request function active in pin 0 = interrupt request function inactive in pin oscopt1 and oscopt0 ? selection bits for oscillator option (0, 0) internal oscillator (0, 1) external oscillator (1, 0) external rc oscillator (1, 1) external xtal oscillator rsten ? rst pin function selection 1 = reset function active in pin 0 = reset function inactive in pin note: the rsten bit is cleared by a power-on re set (por) only. other resets will leave this bit unaffected. coprs (out of stop mode) ? cop reset period selection bit 1 = cop reset short cycle = (2 13 ? 2 4 ) busclkx4 0 = cop reset long cycle = (2 18 ? 2 4 ) busclkx4 coprs (in stop mode) ? auto wakeup period selection bit 1 = auto wakeup short cycle = (2 9 ) intrcosc 0 = auto wakeup long cycle = (2 14 ) intrcosc lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvistop bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode address: $001f bit 7 6 5 4 3 2 1 bit 0 read: coprs lvistop lvirstd lvipwrd lvdlvr ssrec stop copd write: reset:0000u000 por: 00000000 u = unaffected figure 5-2. configuration register 1 (config1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) functional description mc68hc908qf4 ? rev. 1.0 data sheet motorola configuration register (config) 53 lvirstd ? lvi reset disable bit lvirstd disables the reset signal fr om the lvi module. unlike other configuration bits, the lvirstd can be written at any time. 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. 1 = lvi module power disabled 0 = lvi module power enabled lvdlvr ? low voltage detect or low voltage reset mode bit lvdlvr selects the trip voltage of the lvi module. lvd trip voltage can be used as a low voltage warning, while lvr will commonly be used as a reset condition. unlike other config bits, lvdlvr can be written multiple times after reset. 1 = lvi trip voltage level set to lvd trip voltage 0 = lvi trip voltage level set to lvr trip voltage note: the lvdlvr bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 busclkx4 cycles instead of a 4096 busclkx4 cycle delay. 1 = stop mode recovery after 32 busclkx4 cycles 0 = stop mode recovery after 4096 busclkx4 cycles note: exiting stop mode by an lvi reset will result in the long stop recovery. when using the lvi during normal operati on but disabling during stop mode, the lvi will have an enable time of t en . the system stabilization time for power-on reset and long stop recovery (both 4096 busclkx4 cycles) gives a delay longer than the lvi enable time for these startup scenarios. there is no period where the mcu is not protected from a low-power condition. however, when using the short stop recovery configur ation option, the 32 busclkx4 delay must be greater than the lvi?s turn on time to avoid a period in startup where the lvi is not protecting the mcu. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) data sheet mc68hc908qf4 ? rev. 1.0 54 configuration register (config) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola computer operating properly (cop) 55 data sheet ? mc68hc908qf4 section 6. computer op erating properly (cop) 6.1 introduction the computer operating properly (cop) m odule contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop module can be dis abled through the copd bit in the configuration 1 (config1) register. 6.2 functional description figure 6-1. cop block diagram copctl write busclkx4 reset circuit reset status register internal reset sources 12-bit sim counter clear all stages 6-bit cop counter cop disable (from config1) reset copctl write clear copen (from sim) cop counter cop clock cop timeout stop instruction cop rate select (coprs from config1) clear stages 5?12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68hc908qf4 ? rev. 1.0 56 computer operating properly (cop) motorola the cop counter is a free-running 6-bit counter preceded by the 12-bit system integration module (sim) counter. if no t cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 busclkx4 cycles; depending on the state of the cop rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 busclkx4 cycle overflow option, the internal 12.8-mhz oscillator gives a cop timeout period of 20.48 ms. writing any value to location $ffff before an overfl ow occurs prevents a cop reset by clearing the cop counter and stages 12?5 of the sim counter. note: service the cop immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low (if the rsten bit is set in the config1 register) for 32 busclkx4 cycles and sets the cop bit in the reset status register (rsr). see 14.8.1 sim reset status register . note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subrouti ne could keep the cop from generating a reset even while the main program is not working properly. 6.3 i/o signals the following paragraphs describe the signals shown in figure 6-1 . 6.3.1 busclkx4 busclkx4 is the oscillator output signal . busclkx4 frequency is equal to the crystal frequency or the rc-oscillator frequency. 6.3.2 stop instruction the stop instruction clears the sim counter. 6.3.3 copctl write writing any value to the cop control register (copctl) (see 6.4 cop control register ) clears the cop counter and clears stages 12?5 of the sim counter. reading the cop control register returns the low byte of the reset vector. 6.3.4 power-on reset the power-on reset (por) circuit in the sim clears the sim counter 4096 busclkx4 cycles after power up. 6.3.5 internal reset an internal reset clears the sim counter and the cop counter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) cop control register mc68hc908qf4 ? rev. 1.0 data sheet motorola computer operating properly (cop) 57 6.3.6 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the configuration register (config). see section 5. configuration register (config) . 6.3.7 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register 1 (config1). see section 5. configuration register (config) . 6.4 cop cont rol register the cop control register (copctl) is lo cated at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 6.5 interrupts the cop does not generate cpu interrupt requests. 6.6 monitor mode the cop is disabled in monitor mode when v tst is present on the irq pin. 6.7 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.7.1 wait mode the cop continues to operate during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 6-2. cop control register (copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68hc908qf4 ? rev. 1.0 58 computer operating properly (cop) motorola 6.7.2 stop mode stop mode turns off the busclkx4 input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. 6.8 cop module during break mode the cop is disabled during a break inte rrupt with monitor mode when bdcop bit is set in break auxiliary register (brkar). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola central processor unit (cpu) 59 data sheet ? mc68hc908qf4 section 7. central processor unit (cpu) 7.1 introduction the m68hc08 cpu (central processo r unit) is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 7.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908qf4 ? rev. 1.0 60 central processor unit (cpu) motorola 7.3 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 7-1. cpu registers 7.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the re sults of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc908qf4 ? rev. 1.0 data sheet motorola central processor unit (cpu) 61 7.3.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regist er, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes , the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. 7.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack point er decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an i ndex register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note: the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x) bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 7-4. stack pointer (sp) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908qf4 ? rev. 1.0 62 central processor unit (cpu) motorola 7.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automati cally increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. 7.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc) bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 7-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc908qf4 ? rev. 1.0 data sheet motorola central processor unit (cpu) 63 h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, t he highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908qf4 ? rev. 1.0 64 central processor unit (cpu) motorola 7.4 arithmetic/ logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 7.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock 7.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from st op mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 7.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908qf4 ? rev. 1.0 data sheet motorola central processor unit (cpu) 65 7.7 instruction set summary table 7-1 provides a summary of the m68hc08 instruction set. table 7-1. instruction set summary (sheet 1 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908qf4 ? rev. 1.0 66 central processor unit (cpu) motorola bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 table 7-1. instruction set summary (sheet 2 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908qf4 ? rev. 1.0 data sheet motorola central processor unit (cpu) 67 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 table 7-1. instruction set summary (sheet 3 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908qf4 ? rev. 1.0 68 central processor unit (cpu) motorola cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 4 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908qf4 ? rev. 1.0 data sheet motorola central processor unit (cpu) 69 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 table 7-1. instruction set summary (sheet 5 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908qf4 ? rev. 1.0 70 central processor unit (cpu) motorola rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 6 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68hc908qf4 ? rev. 1.0 data sheet motorola central processor unit (cpu) 71 7.8 opcode map see table 7-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack point er 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increm ent addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 7-1. instruction set summary (sheet 7 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc908qf4 ? rev. 1.0 72 central processor unit (cpu) motorola central processor unit (cpu) table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola external interrupt (irq) 73 data sheet ? mc68hc908qf4 section 8. external interrupt (irq) 8.1 introduction the irq pin (external interrupt), shared wi th pta2 (general purpose input) and keyboard interrupt (kbi), provides a maskable interrupt input. 8.2 features features of the irq module include the following: external interrupt pin, irq irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge selectable internal pullup resistor 8.3 functional description irq pin functionality is enabled by setting configuration register 2 (config2) irqen bit accordingly. a zero disables the irq function and irq will assume the other shared functionalities. a one enables the irq function. a falling edge on the external interrupt pi n can latch a central processor unit (cpu) interrupt request. figure 8-2 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (intscr). writing a 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge-triggered out of reset and is software-configurable to be either fa lling-edge or falling-edge and low-level triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when the interrupt pin is edge-triggered only (mode = 0), the cpu interrupt request remains set until a vector fetc h, software clear, or reset occurs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68hc908qf4 ? rev. 1.0 74 external interrupt (irq) motorola figure 8-1. block diagram highlighting irq block and pins v cc mode pllen data bs op1 gnd rext xtal1 xtal0 upclk pfd uhf transmitter rst , irq : pins have internal (about 30k ohms) pull up pta[0:5]: high current si nk and source capability pta[0:5]: pins have programmabl e keyboard interrupt and pull up pta0/ad0/tch0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 16-bit timer module cop module monitor rom ptb0 ptb ddrb m68hc08 cpu pta ddra ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb7 8-bit adc 128 bytes ram power supply v dd v ss mc68hc908qf4 4096 bytes user flash f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) functional description mc68hc908qf4 ? rev. 1.0 data sheet motorola external interrupt (irq) 75 figure 8-2. irq module block diagram when the interrupt pin is both falling-edge and low-level triggered (mode = 1), the cpu interrupt request remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the intscr mask all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the imask bit is clear. note: the interrupt mask (i) in the condition c ode register (ccr) masks all interrupt requests, including external interrupt requests. see 14.6 exception control . figure 8-3 provides a summary of the irq i/o register. ack imask dq ck clr irq high interrupt to mode select logic irq ff request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd internal pullup device irq irqpud addr.register name bit 7654321bit 0 $001d irq status and control register (intscr) see page 77. read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 8-3. irq i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68hc908qf4 ? rev. 1.0 76 external interrupt (irq) motorola 8.4 irq pin a falling edge on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge sensitive and low-level sensitive. with mode set, both of the fo llowing actions must occur to clear irq: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the ack bit in the interrupt status and control register (intscr). the ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software clear and the return of the irq pin to logic 1 may occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge sens itive only. with mode clear, a vector fetch or software cl ear immediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. note: when the irq function is enabled in the config2 register, the bih and bil instructions can be used to read the logic level on the irq pin. if the irq function is disabled, these instructio ns will behave as if the irq pin is a logic 1, regardless of the actual level on the pin. conversely, when the irq function is enabled, bit 2 of the port a data register will always read a 0. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. an internal pullup resistor to v dd is connected to the irq pin; this can be disabled by setting the irqpud bit in the config2 register ($001e). 8.5 irq module during break interrupts the system integration module (sim) c ontrols whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. see section 14. system integration module (sim) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) irq status and control register mc68hc908qf4 ? rev. 1.0 data sheet motorola external interrupt (irq) 77 to allow software to clear the irq latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latches during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. 8.6 irq status an d control register the irq status and control register (iscr) controls and monitors operation of the irq module, see section 5. configuration register (config) . the iscr has the following functions: shows the state of the irq flag clears the irq latch masks irq and interrupt request controls triggering sensitivity of the irq interrupt pin irqf ? irq flag this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. ack always reads as 0. reset clears ack. imask ? irq interrupt mask bit writing a 1 to this read/write bit disabl es irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001d bit 7654321bit 0 read:0000irqf imask mode write: ack reset:00000000 = unimplemented figure 8-4. irq status and control register (intscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68hc908qf4 ? rev. 1.0 78 external interrupt (irq) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola keyboard inte rrupt module (kbi) 79 data sheet ? mc68hc908qf4 section 9. keyboard in terrupt module (kbi) 9.1 introduction the keyboard interrupt module (kbi) prov ides six independently maskable external interrupts, which are accessible via the pta0?pta5 pins. 9.2 features features of the keyboard interrupt module include: six keyboard interrupt pins with s eparate keyboard interrupt enable bits and one keyboard interrupt mask software configurable pullup device if in put pin is configured as input port bit programmable edge-only or edge and level interrupt sensitivity exit from low-power modes figure 9-1 provides a summary of the input/output (i/o) registers addr.register name bit 7654321bit 0 $001a keyboard status and control register (kbscr) see page 84. read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) see page 85. read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 9-1. kbi i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrup t module (kbi) data sheet mc68hc908qf4 ? rev. 1.0 80 keyboard interrupt module (kbi) motorola figure 9-2. block diagram highlighting kbi block and pins v cc mode pllen data bs op1 gnd rext xtal1 xtal0 upclk pfd uhf transmitter rst , irq : pins have internal (about 30k ohms) pull up pta[0:5]: high current sink and source capability pta[0:5]: pins have programmable keyboard interrupt and pull up pta0/ad0/tch0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 16-bit timer module cop module monitor rom ptb0 ptb ddrb m68hc08 cpu pta ddra ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb7 8-bit adc 128 bytes ram power supply v dd v ss mc68hc908qf4 4096 bytes user flash f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) functional description mc68hc908qf4 ? rev. 1.0 data sheet motorola keyboard inte rrupt module (kbi) 81 figure 9-3. keyboard interrupt block diagram 9.3 functional description the keyboard interrupt module controls the enabling/disabling of interrupt functions on the six port a pins. thes e six pins can be enabled/disabled independently of each other. 9.3.1 keyboard operation writing to the kbie0?kbie5 bits in the keyboard interrupt enable register (kbier) independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin in port a also enables its internal pullup device irrespective of ptapuex bits in the port a input pullup enable register (see 13.2.3 port a input pullup enable register ). a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyboard interrupt inputs goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sens itive only, a falling edge on a keyboard interrupt input does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one input because another input is still low, software can disable the latter input while it is low. if the keyboard interrupt is falling edge and low-level sensitive, an interrupt request is present as long as any keyboard interrupt input is low. kbie0 kbie5 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi5 kbi0 synchronizer keyf keyboard interrupt request to pullup enable awuireq (1) to pullup enable 1. for awugen logic refer to figure 4-2. auto wakeup interrupt request generation logic . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrup t module (kbi) data sheet mc68hc908qf4 ? rev. 1.0 82 keyboard interrupt module (kbi) motorola if the modek bit is set, the keyboard interrupt inputs are both falling edge and low-level sensitive, and both of the followi ng actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the interrupt acknowledge signal by writing a 1 to the ackk bit in the keyboard status and control register (kbscr). the ackk bit is useful in applications that poll the keyboard interrupt inputs and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subs equent transitions on the keyboard interrupt inputs. a falling edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the central proc essor unit (cpu) loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interr upt inputs to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the auto wakeup interrupt input, awuireq, will be cleared only by writing to ackk bit in kbscr or reset. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard in terrupt pin is falling-edge sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt input stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists . the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and then read the data register. note: setting a keyboard interrupt enable bit (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) wait mode mc68hc908qf4 ? rev. 1.0 data sheet motorola keyboard inte rrupt module (kbi) 83 9.3.2 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. therefore a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard st atus and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in the data direction register a. 2. write 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 9.4 wait mode the keyboard module remains ac tive in wait mode. cleari ng the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 9.5 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 9.6 keyboard module du ring break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrup t module (kbi) data sheet mc68hc908qf4 ? rev. 1.0 84 keyboard interrupt module (kbi) motorola to protect the latch during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. 9.7 input/output registers the following i/o registers control and m onitor operation of the keyboard interrupt module: keyboard interrupt status and control register (kbscr) keyboard interrupt enable register (kbier) 9.7.1 keyboard status and control register the keyboard status and control register (kbscr): flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port a or auto wakeup. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard interrupt request on port a and auto wakeup logic. ackk always reads as 0. reset clears ackk. address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 9-4. keyboard status and control register (kbscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) input/output registers mc68hc908qf4 ? rev. 1.0 data sheet motorola keyboard inte rrupt module (kbi) 85 imaskk? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port a or auto wakeup. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port a and auto wakeup. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 9.7.2 keyboard interrupt enable register the port a keyboard interrupt enable regist er (kbier) enables or disables each port a pin or auto wakeup to operate as a keyboard interrupt input. kbie5?kbie0 ? port a keyboard interrupt enable bits each of these read/write bits enables the corresponding keyboard interrupt pin on port a to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = kbix pin enabled as keyboard interrupt pin 0 = kbix pin not enabled as keyboard interrupt pin note: awuie bit is not used in conjunction with the keyboard interrupt feature. to see a description of this bit, see section 4. auto wakeup module (awu) . address: $001b bit 7654321bit 0 read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 9-5. keyboard interrupt enable register (kbier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrup t module (kbi) data sheet mc68hc908qf4 ? rev. 1.0 86 keyboard interrupt module (kbi) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola low-voltage inhibit (lvi) 87 data sheet ? mc68hc908qf4 section 10. low-volt age inhibit (lvi) 10.1 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lvi trip falling voltage, v tripf . 10.2 features features of the lvi module include: programmable lvi reset programmable power consumption selectable lvi trip voltage programmable stop mode operation 10.3 functional description figure 10-1 shows the structure of the lvi module. lvistop, lvipwrd, lvdlvr, and lvirstd are user selectabl e options found in the configuration register (config1). see section 5. configuration register (config) . figure 10-1. lvi module block diagram low v dd detector lvipwrd stop instruction lvistop lvi reset lviout v dd > lvitrip = 0 v dd lvitrip = 1 from config from config v dd from config lvirstd lvdlvr from config f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) data sheet mc68hc908qf4 ? rev. 1.0 88 low-voltage inhibit (lvi) motorola the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator. clearing the lvi power disable bit (lvipwrd) enables the lvi to monitor v dd voltage. clearing the lvi reset disable bit (lvirstd) enables the lvi module to generate a reset when v dd falls below a voltage, v tripf or v dtripf . setting the lvi enable in stop mode bit (lvistop) enables the lvi to operate in stop mode. setting the lvd or lvr trip point bit (lvdlvr) selects the lvd trip point voltage. the actual trip thresholds are specified in 17.5 dc electrical characteristics . either trip level can be used as a detect or reset. note: after a power-on reset, the lvi?s default mode of operation is lvr trip voltage. if a higher trip voltage is desired, the user mu st set the lvdlvr bit to raise the trip point to the lvd voltage. if the user requires the higher trip voltage and sets the lvdlvr bit after power-on reset while the vdd supply is not above the v tripr for lvd mode, the microcontroller unit (mcu) will immediately go into reset. the next time the lvi releases the reset, the supply will be above the v tripr for lvd mode. once an lvi reset o ccurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see section 14. system integration module (sim) for the reset recovery sequence. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr) and can be used for polling lvi operation when the lvi reset is disabled. 10.3.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bit. in the configuration register, the lvipwrd bit must be cleared to enable the lvi module, and the lvirstd bit must be set to disable lvi resets. 10.3.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the configuration register, the lvipwrd and lvirstd bits must be cleared to enable the lvi module and to enable lvi resets. 10.3.3 voltage hysteresis protection once the lvi has triggered (by having v dd fall below v tripf ), the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is co ntinually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) lvi status register mc68hc908qf4 ? rev. 1.0 data sheet motorola low-voltage inhibit (lvi) 89 10.3.4 lvi trip selection the lvdlvr bit in the configuration register selects whether the lvi is configured for lvd (low voltage detect) or lvr (low voltage reset) protection. the lvd trip voltage can be used as a low voltage warning. the lvr trip voltage will commonly be configured as a reset condition since it is very close to the minimum operating voltage of the device. the lvdlvr bit can be written to anytime so that battery applications can make use of the lvi as both a warning indicator and to generate a system reset. polling and forced reset operation modes ca n be combined to take full advantage of lvd and lvr trip voltages selection. lvd (lvdlvr = 1) in polling mode (lvirstd = 1) can be used as a low voltage warning in a slowly and continuously falling v dd application (for example, battery applications). once lvd has been identified, the part can be set to lvr (lvdlvr = 0) and reset enabled (lvirstd = 0). so, as v dd continues to fall the part will reset when lvr trip voltage is reached. unlike other bits in config registers, lvirstd and lvdlvr bits are allowed to be written multiple times after reset. note: the microcontroller is guaranteed to operate at a minimum supply voltage. the trip point (v tripf [lvd] or v tripf [lvr]) may be lower than this. see 17.5 dc electrical characteristics for the actual trip point voltages. 10.4 lvi status register the lvi status register (lvisr) indicates if the v dd voltage was detected below the v tripf level while lvi resets have been disabled . lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage and is cleared when v dd voltage rises above v tripr . the difference in these threshold levels results in a hyst eresis that prevents oscillation into and out of reset (see table 10-1 ). reset clears the lviout bit. address: $fe0c bit 7654321bit 0 read:lviout000000r write: reset:00000000 = unimplemented r = reserved figure 10-2. lvi status register (lvisr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) data sheet mc68hc908qf4 ? rev. 1.0 90 low-voltage inhibit (lvi) motorola 10.5 lvi interrupts the lvi module does not generate interrupt requests. 10.6 low-power modes the stop and wait instructions put the mcu in low power-consumption standby modes. 10.6.1 wait mode if enabled, the lvi module remains active in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 10.6.2 stop mode when the lvipwrd bit in the configurati on register is cleared and the lvistop bit in the configuration register is set, th e lvi module remains active in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. table 10-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola oscillator module (osc) 91 data sheet ? mc68hc908qf4 section 11. oscillator module (osc) 11.1 introduction the oscillator module is used to pr ovide a stable clock source for the microcontroller system and bus. the os cillator module generates two output clocks, busclkx2 and busclkx4. the bu sclkx4 clock is used by the system integration module (sim) and the computer operating properly module (cop). the busclkx2 clock is divided by two in the sim to be used as the bus clock for the microcontroller. therefore the bus frequency will be one forth of the busclkx4 frequency. 11.2 features the oscillator has these four clock source options available: 1. internal oscillator: an internally gene rated, fixed frequency clock, trimmable to 5%. this is the default option out of reset. 2. external oscillator: an external clock that can be driven directly into osc1. 3. external rc: a built-in oscillator mo dule (rc oscillator) that requires an external r connection only. the capacitor is internal to the chip. 4. external crystal: a built-in oscillator module (xtal oscillator) that requires an external crystal or ceramic-resonator. 11.3 functional description the oscillator contains these major subsystems: internal oscillator circuit internal or external clock switch control external clock circuit external crystal circuit external rc clock circuit 11.3.1 internal oscillator the internal oscillator circuit is designed for use with no external components to provide a clock source with tolerance less than 25% untrimmed. an 8-bit trimming register allows adjustment to a tolerance of less than 5%. the internal oscillator will generate a cl ock of 4.0 mhz typical (intclk) resulting in a bus speed (internal clock 4) of 1.0 mhz. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator module (osc) data sheet mc68hc908qf4 ? rev. 1.0 92 oscillator module (osc) motorola figure 11-1. block diagram highlighting osc block and pins v cc mode pllen data bs op1 gnd rext xtal1 xtal0 upclk pfd uhf transmitter rst , irq : pins have internal (about 30k ohms) pull up pta[0:5]: high current sink and source capability pta[0:5]: pins have programmable keyboard interrupt and pull up pta0/ad0/tch0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 16-bit timer module cop module monitor rom ptb0 ptb ddrb m68hc08 cpu pta ddra ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb7 8-bit adc 128 bytes ram power supply v dd v ss mc68hc908qf4 4096 bytes user flash f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator module (osc) functional description mc68hc908qf4 ? rev. 1.0 data sheet motorola oscillator module (osc) 93 figure 11-3 shows how busclkx4 is derived from intclk and, like the rc oscillator, osc2 can output busclkx4 by setting osc2en in ptapue register. see section 13. input/output (i/o) ports . 11.3.1.1 internal oscillator trimming the 8-bit trimming register, osctrim, a llows a clock period adjust of +127 and ?128 steps. increasing osctrim value increases the clock period. trimming allows the internal clock frequency to be set to 4.0 mhz 5%. all devices are programmed with a trim value in a reserved flash location, $ffc0. this value can be copied from the flash to the osctrim register ($0038) during reset initialization. reset loads osctrim with a default value of $80. warning: bulk flash erasure will set location $ffc0 to $ff and the factory programmed value will be lost. 11.3.1.2 internal to external clock switching when external clock source (external osc, rc, or xtal) is desired, the user must perform the following steps: 1. for external crystal circuits only, oscopt[1:0] = 1:1: to help precharge an external crystal oscillator, set pta4 (osc2) as an output and drive high for several cycles. this may help the cr ystal circuit start more robustly. 2. set config2 bits oscopt[1:0] according to 11.7 config2 options . the oscillator module control logic will then set osc1 as an external clock input and, if the external crystal option is se lected, osc2 will also be set as the clock output. 3. create a software delay to wait the stabilization time needed for the selected clock source (crystal, resonator, rc ) as recommended by the component manufacturer. a good rule of thumb for crystal oscillators is to wait 4096 cycles of the crystal frequency, i.e., for a 4-mhz crystal, wait approximately 1 msec. 4. after the manufacturer?s recommended delay has elapsed, the ecgon bit in the osc status register (oscstat) needs to be set by the user software. 5. after ecgon set is detected, the osc module checks for o scillator activity by waiting two external clock rising edges. 6. the osc module then switches to the ex ternal clock. logic provides a glitch free transition. 7. the osc module first sets the ecgst bit in the oscstat register and then stops the internal oscillator. note: once transition to the external clock is done, the internal oscillator will only be reactivated with reset. no post-switch cloc k monitor feature is implemented (clock does not switch back to internal if external clock dies). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator module (osc) data sheet mc68hc908qf4 ? rev. 1.0 94 oscillator module (osc) motorola 11.3.2 external oscillator the external clock option is designed for us e when a clock signal is available in the application to provide a clock source to the microcontroller. the osc1 pin is enabled as an input by the oscillator modul e. the clock signal is used directly to create busclkx4 and also divided by two to create busclkx2. in this configuration, the osc2 pin cannot output busclkx4. so the osc2en bit in the port a pullup enable register will be clear to enable pta4 i/o functions on the pin. 11.3.3 xtal oscillator the xtal oscillator circuit is designed for use with an external low-frequency crystal or ceramic resonator to provide an accurate clock source. in this configuration, the osc2 pin is dedicated to the external crystal circuit. the osc2en bit in the port a pullup enable regi ster has no effect when this clock mode is selected. in its typical configuration, the xtal osci llator is connected in a pierce oscillator configuration, as shown in figure 11-2 . this figure shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s figure 11-2. xtal oscillator external connections c 1 c 2 simoscen xtalclk r b x 1 r s mcu from sim osc2 osc1 2 busclkx2 busclkx4 to sim to sim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator module (osc) oscillator module signals mc68hc908qf4 ? rev. 1.0 data sheet motorola oscillator module (osc) 95 11.3.4 rc oscillator the rc oscillator circuit is designed for use with external r to provide a clock source with tolerance less than 25%. in its typical configuration, the rc oscillator requires two external components, one r and one c. in the mc68hlc908qf4, the c apacitor is internal to the chip. the r value should have a tolerance of 1% or less, to obtain a clock source with less than 25% tolerance. the oscillator configuration uses one component, r ext . in this configuration, the osc2 pin can be left in the reset state as pta4. or, the osc2en bit in the port a pullup enable register can be set to enable the osc2 output function on the pin. enabling the osc2 output slightly increases the external rc oscillator frequency, f rcclk . figure 11-3. rc oscillator external connections 11.4 oscillator module signals the following paragraphs describe the signal s that are inputs to and outputs from the oscillator module. 11.4.1 crystal amplifier input pin (osc1) the osc1 pin is either an input to the crystal oscillator amplifier, an input to the rc oscillator circuit, or an external clock source. mcu r ext simoscen osc1 external rc oscillator en rcclk 2 busclkx2 busclkx4 to sim from sim v dd pta4 i/o 1 0 pta4 osc2en pta4/busclkx4 (osc2) to sim see section 17. electrical specifications for component value requirements. 0 1 intclk oscrcopt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator module (osc) data sheet mc68hc908qf4 ? rev. 1.0 96 oscillator module (osc) motorola for the internal oscillator configuration, the osc1 pin can assume other functions according to table 1-1. pin functions . 11.4.2 crystal amplifier output pin (osc2/pta4/busclkx4) for the xtal oscillator device , the osc2 pin is the cr ystal oscillator inverting amplifier output. for the external clock option, the osc2 pin is dedicated to the pta4 i/o function. the osc2en bit has no effect. for the internal oscillator or rc oscillat or options, the osc2 pin can assume other functions according to table 1-1. pin functions , or the output of the oscillator clock (busclkx4). 11.4.3 oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables/disables either the xtal oscillator circuit, the rc oscillator, or the internal oscillator. 11.4.4 xtal oscillator clock (xtalclk) xtalclk is the xtal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 11-2 shows only the logical relation of xtalclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of xtalclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of xtalclk can be unstable at start up. 11.4.5 rc oscillator clock (rcclk) rcclk is the rc oscillator output signal. its frequency is directly proportional to the time constant of external r and internal c. figure 11-3 shows only the logical relation of rcclk to osc1 and may not represent the actual circuitry. table 11-1. osc2 pin function option osc2 pin function xtal oscillator inverting osc1 external clock pta4 i/o internal oscillator or rc oscillator controlled by osc2en bit in ptapue register osc2en = 0: pta4 i/o osc2en = 1: busclkx4 output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator module (osc) low power modes mc68hc908qf4 ? rev. 1.0 data sheet motorola oscillator module (osc) 97 11.4.6 internal oscillator clock (intclk) intclk is the internal oscillator output signal. its nominal frequency is fixed to 4.0 mhz, but it can be also trimmed using th e oscillator trimming feature of the osctrim register (see 11.3.1.1 internal oscillator trimming ). 11.4.7 oscillator out 2 (busclkx4) busclkx4 is the same as the input cl ock (xtalclk, rcclk, or intclk). this signal is driven to the sim module and is used to determine the cop cycles. 11.4.8 oscillator out (busclkx2) the frequency of this signal is equal to hal f of the busclkx4, this signal is driven to the sim for generation of the bus clocks used by the cpu and other modules on the mcu. busclkx2 will be divided again in the sim and results in the internal bus frequency being one fourth of either the xtalclk, rcclk, or intclk frequency. 11.5 low power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 11.5.1 wait mode the wait instruction has no effect on the oscillator logic. busclkx2 and busclkx4 continue to drive to the sim module. 11.5.2 stop mode the stop instruction disables either the xtalclk, the rcclk, or intclk output, hence busclkx2 and busclkx4. 11.6 oscillator during break mode the oscillator continues to drive busclkx2 and busclkx4 when the device enters the break state. 11.7 config2 options two config2 register options affect the operation of the oscillator module: oscopt1 and oscopt0. all config2 r egister bits will have a default configuration. refer to section 5. configuration register (config) for more information on how the config2 register is used. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator module (osc) data sheet mc68hc908qf4 ? rev. 1.0 98 oscillator module (osc) motorola table 11-2 shows how the oscopt bits are used to select the oscillator clock source. 11.8 input/output (i/o) registers the oscillator module contains these two registers: 1. oscillator status register (oscstat) 2. oscillator trim register (osctrim) 11.8.1 oscillator status register the oscillator status register (oscstat) contains the bits for switching from internal to external clock sources. ecgon ? external clock generator on bit this read/write bit enables external clock generator, so that the switching process can be initiated. this bit is forc ed low during reset. this bit is ignored in monitor mode with the internal oscillator bypassed. 1 = external clock generator enabled 0 = external clock generator disabled ecgst ? external clock status bit this read-only bit indicates whether or not an external clock source is engaged to drive the system clock. 1 = an external clock source engaged 0 = an external clock source disengaged table 11-2. oscillator modes oscopt1 oscopt0 oscillator modes 0 0 internal oscillator 0 1 external oscillator 10external rc 1 1 external crystal address: $0036 bit 7654321bit 0 read: rrrrrrecgon ecgst write: reset:00000000 r =reserved = unimplemented figure 11-4. oscillator status register (oscstat) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator module (osc) input/output (i/o) registers mc68hc908qf4 ? rev. 1.0 data sheet motorola oscillator module (osc) 99 11.8.2 oscillator trim register (osctrim) trim7?trim0 ? internal osc illator trim factor bits these read/write bits change the size of the internal capacitor used by the internal oscillator. by measuring the per iod of the internal clock and adjusting this factor accordingly, the frequency of the internal clock can be fine tuned. increasing (decreasing) this factor by one increases (decreases) the period by approximately 0.2% of the untrimmed period (the period for trim = $80). the trimmed frequency is guaranteed not to vary by more than 5% over the full specified range of temperature and voltage. the reset value is $80, which sets the frequency to 4.0 mhz (1.0 mhz bus speed) 25%. address: $0038 bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 figure 11-5. oscillator trim register (osctrim) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator module (osc) data sheet mc68hc908qf4 ? rev. 1.0 100 oscillator module (osc) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola pll tuned uhf transmitter module 101 data sheet ? mc68hc908qf4 section 12. pll tuned uhf transmitter module 12.1 introduction this section describes the integrated ra dio frequency (rf) module. this module integrates an ultra high frequency (uhf) transmitter offering these key features: switchable frequency bands: 315, 434, and 868 mhz on/off keying (ook) and frequenc y shift keying (fsk) modulation adjustable output power range fully integrated voltage-c ontrolled oscillator (vco) supply voltage range: 1.9 to 3.6 v very low standby current: 0.1 na @ t a = 25 c low supply voltage shutdown data clock output for microcontroller low external component count architecture of the module is described in figure 12-1 . figure 12-1. simplified integrated rf module block diagram vco first order pfd 32 2 pa xco 64 control driver enable enable_fsk data_ook data_fsk cfsk xtal0 xtal1 mode data enable v cc gnd band r ext gndrf rfout dataclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pll tuned uhf transmitter module data sheet mc68hc908qf4 ? rev. 1.0 102 pll tuned uhf transmitter module motorola figure 12-2. block diagram highlighting pll tuned uhf transmitter block and pins v cc mode pllen data bs op1 gnd rext xtal1 xtal0 upclk pfd uhf transmitter rst , irq : pins have internal (about 30k ohms) pull up pta[0:5]: high current si nk and source capability pta[0:5]: pins have programmabl e keyboard interrupt and pull up pta0/ad0/tch0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 16-bit timer module cop module monitor rom ptb0 ptb ddrb m68hc08 cpu pta ddra ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb7 8-bit adc 128 bytes ram power supply v dd v ss mc68hc908qf4 4096 bytes user flash f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pll tuned uhf transmitter module transmitter functional description mc68hc908qf4 ? rev. 1.0 data sheet motorola pll tuned uhf transmitter module 103 12.2 transmitter fun ctional description the transmitter is a phase-locked loop (p ll) tuned low-power uhf transmitter. the different modes of operation are c ontrolled by the microcontroller through several digital input pins. the power supply voltage ranges from 1.9 v to 3.6 v allowing operation with a single lithium cell. 12.3 phase-lock loop (p ll) and local oscillator the vco is a completely integrated relaxation oscillator. the phase frequency detector (pfd) and the loop filter are fully integrated.the exact output frequency is equal to: f rfout = f xtal x pll divider ratio the frequency band of operation is selected through the band pin. table 12-1 provides details for each frequency band selection. an out-of-lock function is performed by monitoring the internal pfd output voltage. when it exceeds its limits, the rf output stage is disabled. 12.4 rf output stage the output stage is a single-ended square wave switched current source. harmonics will be present in the output current drive. their radiated absolute level depends on the antenna characteristics and output power. typical application demonstrates compliance to european te lecommunications standards institute (etsi) standard. a resistor r ext connected to the rext pin controls the output power allowing a tradeoff between radiated power and current consumption. the output voltage is internally clamped to: v cc 2 v be (typically v cc 1.5 v @ t a = 25 c). table 12-1. frequency band selection and associated divider ratios band input level frequency band (mhz) pll divider ratio crystal oscillator frequency (mhz) high 315 32 9.84 434 13.56 low 868 64 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pll tuned uhf transmitter module data sheet mc68hc908qf4 ? rev. 1.0 104 pll tuned uhf transmitter module motorola 12.5 modulation if a low-logic level is applied on pin mode, then the on/off keying (ook) modulation is selected. this modulation is performed by switching on/off the rf output stage. the logic level applied on pin data controls the output stage state: data = 0 output stage off data = 1 output stage on if a high-logic level is applied on pin mode, then frequency shift keying (fsk) modulation is selected. this modulation is achieved by modulating the frequency of the reference oscillator. this frequency change is performed by switching the external crystal load capacitor. the logic level applied on pin data controls the internal switch connected to pin cfsk: data = 0 switch off data = 1 switch on in case of figure 12-6 , where the two capacitors c6 and c9 are in series: data = 0 leads to the high value of the carrier frequency data = 1 leads to the low value of the carrier frequency this crystal pulling solution implies that the rf output frequency deviation equals the crystal frequency deviation multipled by the pll divider ratio (see table 12-1 ). 12.6 microcontroller interfaces four digital input pins (enable, data , band, and mode) enable the circuit to be controlled by a microcontroller. it is recommended to configure the band frequency and the modulation type befor e enabling the circuit. in a typical application the input pins band and mode are hardwired. one digital output (dataclk) provides th e microcontroller a reference frequency for data clocking. this frequency is equal to the crystal oscillator frequency divided by 64 (see table 12-2 ). table 12-2. dataclk frequency versus crystal oscillator frequency crystal oscillator frequency (mhz) dataclk frequency (khz) 9.84 154 13.56 212 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pll tuned uhf transmitter module state machine mc68hc908qf4 ? rev. 1.0 data sheet motorola pll tuned uhf transmitter module 105 12.7 state machine figure 12-3 details the main state machine. figure 12-3. main state machine enable = 1 state 3 pll acquisition, ready to transmit state 2 pll enabled but out of lock-in range state 1 standby mode enable = 0 power on and enable = 0 state 4 transmission mode state 6 shutdown mode state 5 pll out of lock-in range pll in lock-in range pll out of lock-in range enable = 0 v battery < v shutdoown data pll in lock-in range pll out of lock-in range f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pll tuned uhf transmitter module data sheet mc68hc908qf4 ? rev. 1.0 106 pll tuned uhf transmitter module motorola state 1 the circuit is in standby mode and draw s only a leakage current from the power supply. state 2 in this state, the pll is enabled but out of the lock-in range. therefore the rf output stage is switched off preventing any data transmission. data clock is available on pin dataclk. in normal oper ation, this state is transitional. state 3 in this state, the pll is within the lock-in range. if t < t pll_lock_in , then the pll can still be in acquisition mode. if t t pll_lock_in , then the pll is locked. the circuit is ready to transmit in band and is waiting for the first data (see figure 12-4 ). state 4 a rising edge on pin data starts the transmission. data entered on pin data are output on pin rfout. the modulation is the one selected through the level applied on pin mode. state 5 an out-of-lock condition has been detected. the rf output stage is switched off preventing any data transmission. data clock is available on pin dataclk. state 6 when the supply voltage falls below the shutdown voltage threshold (v sdwn ) the whole circuit is switched off. applying a low level on pin enable is the only condition to get out of this state. figure 12-4 shows the waveforms of the main si gnals for a typical application cycle figure 12-4. signals, waveforms, and timing definitions enable dataclk data rfout state 1 state 2 state 4 state 3 mode = 0, ook modulation mode = 1, fsk modulation state 1 f carrier f carrier f carrier2 f carrier1 f carrier2 f carrier1 t pll_lock_in t dataclk_settling see note note: pll locked, circuit ready to tramsmit in band. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pll tuned uhf transmitter module power management mc68hc908qf4 ? rev. 1.0 data sheet motorola pll tuned uhf transmitter module 107 12.8 power management when the battery voltage falls below the shutdown voltage threshold (v sdwn ) the whole circuit is switched off. note: after this shutdown, the circuit is latched until a low level is applied on pin enable (see state 6 under 12.7 state machine ). 12.9 data clock when the data clock starts, the high-to-lo w ratio may be uneven. similarly the clock is switched off asynchronously so the last period length is not guaranteed. 12.10 applicatio n information this subsection provides application information for the usage of the uhf transmitter module. 12.10.1 application schematics in ook and fsk modulation figure 12-5 and figure 12-6 show application schem atics in ook and fsk modulation for the 315-mhz and 434-mhz frequency bands. for 868-mhz band application, the input pin band must be wi red to gnd. see component description in table 12-4 and table 12-5 . figure 12-5. application schematic in ook modulation, 315-mhz and 434-mhz frequency bands dataclk data band gnd xtal1 xtal0 r ext mode enable v cc gndrf rfout v cc cfsk to mcu v cc c6 y1 r2 nc c7 c8 v cc nc = no connection matching network antenna f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pll tuned uhf transmitter module data sheet mc68hc908qf4 ? rev. 1.0 108 pll tuned uhf transmitter module motorola figure 12-6. application schematic in fsk modulation, 315-mhz and 434-mhz frequency bands table 12-3. component description component function value unit y1 crystal 315-mhz band: 9.84, see table 12-5 mhz 434-mhz band: 13.56, see table 12-5 mhz 868-mhz band: 13.56, see table 12-5 mhz r2 rf output level setting resistor (r ext ) 12 k ? c6 crystal load capacitor ook modulation: 18 pf fsk modulation: 22 pf c7 power supply decoupling capacitor 10 nf c8 100 pf c9 crystal pulling capacitor for fsk modulation only see table 12-5 pf dataclk data band gnd xtal1 xtal0 r ext mode enable v cc gndrf rfout v cc cfsk to mcu v cc y1 r2 c7 c8 matching network antenna v cc c6 c9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pll tuned uhf transmitter module application information mc68hc908qf4 ? rev. 1.0 data sheet motorola pll tuned uhf transmitter module 109 a example of crystal reference is: tokyo denpa tts-3b 13568.750 khz, see table 12-4 . 12.10.2 complete application schematic figure 12-7 gives a complete application schematic using the motorola mc68hc908rf2. ook modulation is selected, f carrier = 433.92 mhz. table 12-4. recommended crystal characteristics (smd ceramic package) parameter value unit load capacitance 20 pf motional capacitance 6.7 ff static capacitance 2 pf loss resistance 40 w table 12-5. crystal pulling capacitor value versus carrier frequency total deviation carrier frequency (mhz) carrier frequency total deviation (khz) capacitor value (pf) 434 40 18 70 10 100 6.8 868 80 18 140 10 200 6.8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pll tuned uhf transmitter module data sheet mc68hc908qf4 ? rev. 1.0 110 pll tuned uhf transmitter module motorola figure 12-7. complete application schematic in ook modulation, 434-mhz frequency band xtal0 xtal1 gnd pta1/tch1/kbi1 ptb2 ptb3 pta2/irq /kbi2/tck pta3/rst /kbi3 y1 c10 18 pf 13.56 mhz r2 12 k c9 2.2 pf c5 100 pf v batt c3 10 nf sw1 sw2 ptb0 v dd v ss ptb1 pta0/tch0/kbi0 dataclk data band pta5/osc1/kbi5 ptb6 ptb7 pta4/osc2/kbi4 ptb5 nc nc ptb4 rext cfsk v cc rfout gnddrf v cc enable mode enable v batt c6 10 nf data data v batt enable dataclk dataclk mc68hc908qf4 2 3 4 5 6 7 8 1 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola input/output (i/o) ports 111 data sheet ? mc68hc908qf4 section 13. input/output (i/o) ports 13.1 introduction the mc68hc908qf4 has thirteen bidirecti onal pins and one input only pin. all i/o pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termin ation for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. figure 13-1 provides a summary of the i/o registers. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 112. read: r awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 115. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 113. read: r r ddra5 ddra4 ddra3 0 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 115. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $000b port a input pullup enable register (ptapue) see page 114. read: osc2en ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000c port b input pullup enable register (ptbpue) see page 116. read: ptbpue7 ptbpue6 ptbpue5 ptbpue4 ptbpue3 ptbpue2 ptbpue1 ptbpue0 write: reset:00000000 r= reserved = unimplemented figure 13-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68hc908qf4 ? rev. 1.0 112 input/output (i/o) ports motorola 13.2 port a port a is a 6-bit special function port that shares all six of its pins with the keyboard interrupt (kbi) module (see section 9. keyboard interrupt module (kbi) ). each port a pin also has a software configurabl e pullup device if the corresponding port pin is configured as an input port. note: pta2 is input only. when the irq function is enabled in the configuration register 2 (config2), bit 2 of the port a data register (pta) will always read a 0. in this case, the bih and bil instructions can be used to read the logic level on the pta2 pin. when the irq function is disabled, these in structions will behave as if the pta2 pin is a logic 1. however, reading bit 2 of pta will read the actual logic level on the pin. 13.2.1 port a data register the port a data register (pta) contains a da ta latch for each of the six port a pins. pta[5:0] ? port a data bits these read/write bits are software progra mmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. awul ? auto wakeup latch data bit this is a read-only bit which has the value of the auto wakeup interrupt request latch. the wakeup request signal is generated internally (see section 4. auto wakeup module (awu) ). there is no pta6 port nor any of the associated bits such as pta6 data register, pullup enable or direction. kbi[5:0] ? port a keyboard interrupts the keyboard interrupt enable bits, kbie5?kbie0, in the keyboard interrupt control enable register (kbier) enable the port a pins as external interrupt pins (see section 9. keyboard interrupt module (kbi) ). address: $0000 bit 7654321bit 0 read: r awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset additional functions: kbi5 kbi4 kbi3 kbi2 kbi1 kbi0 r= reserved = unimplemented figure 13-2. port a data register (pta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port a mc68hc908qf4 ? rev. 1.0 data sheet motorola input/output (i/o) ports 113 13.2.2 data direction register a data direction register a (ddra) determines whether each port a pin is an input or an output. writing a 1 to a ddra bit enab les the output buffer for the corresponding port a pin; a 0 disables the output buffer. ddra[5:0] ? data direction register a bits these read/write bits control port a data direction. reset clears ddra[5:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 13-4 shows the port a i/o logic. figure 13-4. port a i/o circuit note: figure 13-4 does not apply to pta2 when ddrax is a 1, reading address $0000 reads the ptax data latch. when ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. address: $0004 bit 7654321bit 0 read: r r ddra5 ddra4 ddra3 0 ddra1 ddra0 write: reset:00000000 r = reserved = unimplemented figure 13-3. data direction register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus 30 k ptapuex to keyboard interrupt circuit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68hc908qf4 ? rev. 1.0 114 input/output (i/o) ports motorola 13.2.3 port a input pullup enable register the port a input pullup enable register (ptapue) contains a software configurable pullup device for each if the six port a pins . each bit is individually configurable and requires the corresponding data direction register, ddrax, to be configured as input. each pullup device is automatically and dynamically disabled when its corresponding ddrax bit is configured as output. osc2en ? enable pta4 on osc2 pin this read/write bit configures the osc2 pin function when internal oscillator or rc oscillator option is selected. this bit has no effect for the xtal or external oscillator options. 1 = osc2 pin outputs the internal or rc oscillator clock (busclkx4) 0 = osc2 pin configured for pta4 i/o, having all the interrupt and pullup functions ptapue[5:0] ? port a input pullup enable bits these read/write bits are software pr ogrammable to enable pullup devices on port a pins. 1 = corresponding port a pin configured to have internal pull if its ddra bit is set to 0 0 = pullup device is disconnected on t he corresponding port a pin regardless of the state of its ddra bit table 13-1 summarizes the operation of the port a pins. address: $000b bit 7654321bit 0 read: osc2en ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 = unimplemented figure 13-5. port a input pullup enable register (ptapue) table 13-1. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10 x (1) input, v dd (2) ddra5?ddra0 pin pta5?pta0 (3) 00x input, hi-z (4) ddra5?ddra0 pin pta5?pta0 (3) x 1 x output ddra5?ddra0 pta5?pta0 pta5?pta0 (5) 1. x = don?t care 2. i/o pin pulled to v dd by internal pullup. 3. writing affects data regist er, but does not affect input. 4. hi-z = high impedance 5. output does not apply to pta2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port b mc68hc908qf4 ? rev. 1.0 data sheet motorola input/output (i/o) ports 115 13.3 port b port b is an 8-bit general purpose i/o port. 13.3.1 port b data register the port b data register (ptb) contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software progra mmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. 13.3.2 data direction register b data direction register b (ddrb) determines whether each port b pin is an input or an output. writing a 1 to a ddrb bit enab les the output buffer for the corresponding port b pin; a 0 disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 13-8 shows the port b i/o logic. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 13-6. port b data register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 13-7. data direction register b (ddrb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68hc908qf4 ? rev. 1.0 116 input/output (i/o) ports motorola figure 13-8. port b i/o circuit when ddrbx is a 1, reading address $0001 reads the ptbx data latch. when ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-2 summarizes the operation of the port b pins. 13.3.3 port b input pullup enable register the port b input pullup enable register (ptbpue) contains a software configurable pullup device for each of the eight port b pins. each bit is individually configurable and requires the corresponding data direction register, ddrbx, be configured as input. each pullup device is automatically and dynamically disabled when its corresponding ddrbx bit is configured as output. table 13-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb7?ddrb0 pin ptb7?ptb0 (3) 3. writing affects data register, but does not affect the input. 1 x output ddrb7?ddrb0 pin ptb7?ptb0 read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus 30 k ptbpuex address: $000c bit 7654321bit 0 read: ptbpue7 ptbpue6 ptbpue5 ptbpue4 ptbpue3 ptbpue2 ptbpue2 ptbpue0 write: reset: 00000000 figure 13-9. port b input pullup enable register (ptbpue) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port b mc68hc908qf4 ? rev. 1.0 data sheet motorola input/output (i/o) ports 117 ptbpue[7:0] ? port b input pullup enable bits these read/write bits are software pr ogrammable to enable pullup devices on port b pins 1 = corresponding port b pin configured to have internal pull if its ddrb bit is set to 0 0 = pullup device is disconnected on t he corresponding port b pin regardless of the state of its ddrb bit. table 13-3 summarizes the operation of the port b pins. table 13-3. port b pin functions ptbpue bit ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 10 x (1) input, v dd (2) ddrb7?ddrb0 pin ptb7?ptb0 (3) 00x input, hi-z (4) ddrb7?ddrb0 pin ptb7?ptb0 (3) x 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 1. x = don?t care 2. i/o pin pulled to v dd by internal pullup. 3. writing affects data regist er, but does not affect input. 4. hi-z = high impedance f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68hc908qf4 ? rev. 1.0 118 input/output (i/o) ports motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola system integr ation module (sim) 119 data sheet ? mc68hc908qf4 section 14. system inte gration module (sim) 14.1 introduction this section describes the system integr ation module (sim), which supports up to 24 external and/or internal interrupts. together with the central processor unit (cpu), the sim controls all microcontrolle r unit (mcu) activities. a block diagram of the sim is shown in figure 14-1 . figure 14-2 is a summary of the sim i/o registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing 14.2 rst and irq pins initialization rst and irq pins come out of reset as pta3 and pta2 respectively. rst and irq functions can be activated by progr aming config2 accordingly. refer to section 5. configuration register (config) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908qf4 ? rev. 1.0 120 system integration module (sim) motorola figure 14-1. sim block diagram table 14-1. signal name conventions signal name description busclkx4 buffered clock from the internal, rc or xtal oscillator circuit. busclkx2 the busclkx4 frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks (bus clock = busclkx4 4). address bus internal address bus data bus internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) busclkx2 (from oscillator) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock busclkx4 (from oscillator) 2 lvi reset (from lvi module) v dd internal pull-up forced mon mode entry (from menrst module) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim bus clock control and generation mc68hc908qf4 ? rev. 1.0 data sheet motorola system integr ation module (sim) 121 14.3 sim bus clock co ntrol and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, busclkx2, as shown in figure 14-3 . figure 14-3. sim clock signals addr. register name bit 7 6 5 4 3 2 1 bit 0 $fe00 break status register (bsr) see page 161. read: rrrrrr sbsw r write: note 1 reset:00000000 1. writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 135. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 reserved rrrrrrrr $fe03 break flag control register (bfcr) see page 136. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 130. read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 131. read:if140000000 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 131. read:0000000if15 write:rrrrrrrr reset:00000000 = unimplemented r = reserved figure 14-2. sim i/o register summary 2 bus clock generators sim sim counter from oscillator from oscillator busclkx2 busclkx4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908qf4 ? rev. 1.0 122 system integration module (sim) motorola 14.3.1 bus timing in user mode , the internal bus frequency is t he oscillator frequency (busclkx4) divided by four. 14.3.2 clock start-up from por when the power-on reset module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 busclkx4 cycle por time out has completed. the ibus clocks start upon completion of the time out. 14.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt or reset, the sim allows busclkx4 to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay time out. this time out is selectable as 4096 or 32 busclkx4 cycles. see 14.7.2 stop mode . in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wa it mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 14.4 reset and syst em initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 14.5 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). see 14.8 sim registers . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68hc908qf4 ? rev. 1.0 data sheet motorola system integr ation module (sim) 123 14.4.1 external pin reset the rst pin circuits include an internal pullup device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for at least the minimum t rl time. figure 14-4 shows the relative timing. the rst pin function is only available if the rsten bit is set in the config1 register. figure 14-4. external reset timing 14.4.2 active resets from internal sources the rst pin is initially setup as a general- purpose input after a por. setting the rsten bit in the config1 register enables the pin for the reset function. this section assumes the rsten bit is se t when describing activity on the rst pin. all internal reset sources actively pull the rst pin low for 32 busclkx4 cycles to allow resetting of external peripherals. t he internal reset signal irst continues to be asserted for an additional 32 cycles (see figure 14-5 ). an internal reset can be caused by an illegal address, illegal opcode, cop time out, lvi, or por (see figure 14-6 ). note: for por and lvi resets, the sim cycles through 4096 busclkx4 cycles during which the sim forces the rst pin low. the internal re set signal then follows the sequence from the falling edge of rst shown in figure 14-5 . the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. figure 14-5. internal reset timing rst address bus pc vect h vect l busclkx2 irst rst rst pulled low by mcu address 32 cycles 32 cycles vector high busclkx4 bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908qf4 ? rev. 1.0 124 system integration module (sim) motorola figure 14-6. sources of internal reset 14.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power on has occurred. the sim counter counts out 4096 busclkx4 cycles. sixty-four bu sclkx4 cycles later, the cpu and memories are released from reset to al low the reset vector sequence to occur. at power on, the following events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscillator to drive busclkx4. internal clocks to the cpu and modules are held inactive for 4096 busclkx4 cycles to allow stabilization of the oscillator. the por bit of the sim reset status register (srsr) is set. see figure 14-7 . 14.4.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module time out, write any value to location $ffff. writing to location $ffff clears the cop counter and stages 12?5 of the sim counter. the sim counter output, which occurs at least every (2 12 ? 2 4 ) busclkx4 cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time out. the cop module is disabled during a break interrupt with monitor mode when bdcop bit is set in break auxiliary register (brkar). table 14-2. reset recovery timing reset recovery type actual number of cycles por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) illegal address rst illegal opcode rst coprst por lvi internal reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68hc908qf4 ? rev. 1.0 data sheet motorola system integr ation module (sim) 125 figure 14-7. por recovery 14.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the mask option register is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 14.4.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. see figure 2-1. memory map for memory ranges. 14.4.2.5 low-voltage inhibit (lvi) reset the lvi asserts its output to the sim when the v dd voltage falls to the lvi trip voltage v tripf . the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 busclkx4 cycles after v dd rises above v tripr . sixty-four busclkx4 cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. the sim actively pulls down the (rst ) pin for all internal reset sources. porrst osc1 busclkx4 busclkx2 rst address bus 4096 cycles 32 cycles 32 cycles $fffe $ffff (rst pin is a general-purpose input after a por) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908qf4 ? rev. 1.0 126 system integration module (sim) motorola 14.5 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the clock for the cop module. the sim counter is clocked by the falling edge of busclkx4. 14.5.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to driv e the bus clock state machine. 14.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register 1 (config1). if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 busclkx4 cycles down to 32 busclkx4 cy cles. this is ideal for applications using canned oscillators that do not requ ire long start-up times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared in the configur ation register 1 (config1). 14.5.3 sim counter and reset states external reset has no effect on the sim counter (see 14.7.2 stop mode for details.) the sim counter is free-running after all reset states. see 14.4.2 active resets from internal sources for counter control and internal reset recovery sequences. 14.6 exception control normal sequential program execution c an be changed in three different ways: 1. interrupts a. maskable hardware cpu interrupts b. non-maskable software interrupt instruction (swi) 2. reset 3. break interrupts 14.6.1 interrupts an interrupt temporarily changes the sequen ce of program execution to respond to a particular event. figure 14-8 flow charts the handling of system interrupts. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68hc908qf4 ? rev. 1.0 data sheet motorola system integr ation module (sim) 127 figure 14-8. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? irq interrupt? timer interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers execute instruction yes yes stack cpu registers set i bit load pc with interrupt vector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908qf4 ? rev. 1.0 128 system integration module (sim) motorola interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 14-9 shows interrupt entry timing. figure 14-10 shows interrupt recovery timing. figure 14-9 . interrupt entry figure 14-10. interrupt recovery 14.6.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the si m checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. module data bus r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr address bus dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module data bus r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 address bus ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68hc908qf4 ? rev. 1.0 data sheet motorola system integr ation module (sim) 129 if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 14-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 14-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 return-from-interrupt (rti) instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family , the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing m ode, software should save the h register and then restore it prior to exiting the routine. 14.6.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908qf4 ? rev. 1.0 130 system integration module (sim) motorola 14.6.2 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 14-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. 14.6.2.1 interrupt status register 1 if1 and if3?if5 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 14-3 . 1 = interrupt request present 0 = no interrupt request present bit 0, 1, 3, and 7 ? always read 0 table 14-3. interrupt sources priority source flag mask (1) 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. int register flag vector address highest lowest reset ? ? ? $fffe?$ffff swi instruction ? ? ? $fffc?$fffd irq pin irqf imask if1 $fffa?$fffb timer channel 0 interrupt ch0f ch0ie if3 $fff6?$fff7 timer channel 1 interrupt ch1f ch1ie if4 $fff4?$fff5 timer overflow interrupt tof toie if5 $fff2?$fff3 keyboard interrupt keyf imaskk if14 $ffe0?$ffe1 adc conversion complete interrupt coco aien if15 $ffde?$ffdf address: $fe04 bit 7654321bit 0 read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 14-12. interrupt status register 1 (int1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68hc908qf4 ? rev. 1.0 data sheet motorola system integr ation module (sim) 131 14.6.2.2 interrupt status register 2 i f 14 ? interrupt flags this flag indicates the presence of interrupt requests from the sources shown in table 14-3 . 1 = interrupt request present 0 = no interrupt request present bit 0?6 ? always read 0 14.6.2.3 interrupt status register 3 if15 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 14-3 . 1 = interrupt request present 0 = no interrupt request present bit 1?7 ? always read 0 14.6.3 reset all reset sources always have equal and highest priority and cannot be arbitrated. 14.6.4 break interrupts the break module can stop normal prog ram flow at a software programmable break point by asserting its break interrupt output. (see section 16. development support .) the sim puts the cpu into the break state by forcing it to the swi vector address: $fe05 bit 7654321bit 0 read:if140000000 write:rrrrrrrr reset:00000000 r= reserved figure 14-13. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read:0000000if15 write:rrrrrrrr reset:00000000 r= reserved figure 14-14. interrupt status register 3 (int3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908qf4 ? rev. 1.0 132 system integration module (sim) motorola location. refer to the break interrupt s ubsection of each module to see how each module is affected by the break state. 14.6.5 status flag protection in break mode the sim controls whether status flags co ntained in other modules can be cleared during break mode. the user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (bcfe) in the break flag control register (bfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 14.7 low-power modes executing the wait or stop instruction puts the mcu in a low power-consumption mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 14.7.1 wait mode in wait mode, the cpu clocks are inacti ve while the peripheral clocks continue to run. figure 14-15 shows the timing for wait mode entry. figure 14-15. wait mode entry timing wait addr + 1 same same address bus data bus previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes mc68hc908qf4 ? rev. 1.0 data sheet motorola system integr ation module (sim) 133 a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset (or break in emulation mode). a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the break status register (bsr). if the cop disable bit, copd, in the configuration register is 0, then the computer operating proper ly module (cop) is enabled and remains active in wait mode. figure 14-16 and figure 14-17 show the timing for wait recovery. figure 14-16. wait recovery from interrupt figure 14-17. wait recovery from internal reset 14.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 address bus data bus exitstopwait note: exitstopwait = rst pin or cpu interrupt address bus data bus rst (1) $a6 $a6 $6e0b rst vct h rst vct l $a6 busclkx4 32 cycles 32 cycles 1. rst is only available if the rsten bi t in the config1 register is set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908qf4 ? rev. 1.0 134 system integration module (sim) motorola the sim disables the oscillator signal s (busclkx2 and busclkx4) in stop mode, stopping the cpu and peripherals. st op recovery time is selectable using the ssrec bit in the configuration register 1 (config1). if ssrec is set, stop recovery is reduced from the normal del ay of 4096 busclkx4 cycles down to 32. this is ideal for the internal oscillator, rc oscillator, and external oscillator options which do not require long start-up times from stop mode. note: external crystal applications should use t he full stop recovery time by clearing the ssrec bit. the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 14-18 shows stop mode entry timing and figure 14-19 shows the stop mode recovery time from interrupt or break note: to minimize stop current, all pins configur ed as inputs should be driven to a logic 1 or logic 0. figure 14-18. stop mode entry timing figure 14-19. stop mode recovery from interrupt stop addr + 1 same same address bus data bus previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. busclkx4 interrupt address bus stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68hc908qf4 ? rev. 1.0 data sheet motorola system integr ation module (sim) 135 14.8 sim registers the sim has three memory mapped registers. table 14-4 shows the mapping of these registers. 14.8.1 sim reset status register this register contains seven flags that show the source of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (ill egal attempt to fetch an opcode from an unimplemented address) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr table 14-4. sim registers address register access mode $fe00 bsr user $fe01 srsr user $fe03 bfcr user address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 = unimplemented figure 14-20. sim reset status register (srsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908qf4 ? rev. 1.0 136 system integration module (sim) motorola modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $ff after por while irq = v dd 0 = por or read of srsr lvi ? low voltage inhibit reset bit 1 = last reset caused by lvi circuit 0 = por or read of srsr 14.8.2 break flag control register the break control register (bfcr) contai ns a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 14-21. break flag control register (bfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola timer interface module (tim) 137 data sheet ? mc68hc908qf4 section 15. timer inte rface module (tim) 15.1 introduction this section describes the timer interfac e module (tim). the tim is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 15-2 is a block diagram of the tim. 15.2 features features of the tim include the following: two input capture/output compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input ? 7-frequency internal bus clock prescaler selection ? external tim clock input free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits 15.3 pin name conventions the tim shares two input/output (i/o) pins with two port a i/o pins. the full names of the tim i/o pins are listed in table 15-1 . the generic pin name appear in the text that follows. table 15-1. pin name conventions tim generic pin names: tch0 tch1 tclk full tim pin names: pta0/tch0 pta1/tch1 pta2/tclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68hc908qf4 ? rev. 1.0 138 timer interface module (tim) motorola figure 15-1. block diagram highlighting tim block and pins v cc mode pllen data bs op1 gnd rext xtal1 xtal0 upclk pfd uhf transmitter rst , irq : pins have internal (about 30k ohms) pull up pta[0:5]: high current sink and source capability pta[0:5]: pins have programmable keyboard interrupt and pull up pta0/ad0/tch0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 16-bit timer module cop module monitor rom ptb0 ptb ddrb m68hc08 cpu pta ddra ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb7 8-bit adc 128 bytes ram power supply v dd v ss mc68hc908qf4 4096 bytes user flash f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68hc908qf4 ? rev. 1.0 data sheet motorola timer interface module (tim) 139 15.4 functional description figure 15-2 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides t he timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time wi thout affecting the counting sequence. the two tim channels are programmable inde pendently as input capture or output compare channels. figure 15-2. tim block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a internal bus clock tch1 tch0 interrupt logic port logic interrupt logic interrupt logic port logic pta2/irq /kbi2/tclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68hc908qf4 ? rev. 1.0 140 timer interface module (tim) motorola addr. register name bit 7654321bit 0 $0020 tim status and control register (tsc) see page 147. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim counter register high (tcnth) see page 149. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0022 tim counter register low (tcntl) see page 149. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) see page 149. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $0024 tim counter modulo register low (tmodl) see page 149. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $0025 tim channel 0 status and control register (tsc0) see page 150. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim channel 0 register high (tch0h) see page 153. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0027 tim channel 0 register low (tch0l) see page 153. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset $0028 tim channel 1 status and control register (tsc1) see page 150. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim channel 1 register high (tch1h) see page 153. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $002a tim channel 1 register low (tch1l) see page 153. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset = unimplemented figure 15-3. tim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68hc908qf4 ? rev. 1.0 data sheet motorola timer interface module (tim) 141 15.4.1 tim counter prescaler the tim clock source is one of the seven prescaler outputs or the tim clock pin, tclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register (tsc) select the tim clock source. 15.4.2 input capture with the input capture function, the tim ca n capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim central processor unit (cpu) interrupt requests. 15.4.3 output compare with the output compare function, the tim can generate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 15.4.3.1 unbuffere d output compare any output compare channel can generate unbuffered output compare pulses as described in 15.4.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim ch annel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchroni ze unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68hc908qf4 ? rev. 1.0 142 timer interface module (tim) motorola period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 15.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 stat us and control register (tsc0) links channel 0 and channel 1. the output compare value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new val ue to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 15.4.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determines the period of the pwm si gnal. the channel pin toggles when the counter reaches the value in the tim count er modulo registers. the time between overflows is the period of the pwm signal. as figure 15-4 shows, the output compare value in the tim channel registers determines the pulse width of the pw m signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is logic 1 (elsxa = 0). program the tim to set the pin if the state of the pwm pulse is logic 0 (elsxa = 1). the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is 000. see 15.9.1 tim status and control register . the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68hc908qf4 ? rev. 1.0 data sheet motorola timer interface module (tim) 143 figure 15-4. pwm period and pulse width 15.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 15.4.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing t he new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter re aches the old value but after the counter reaches the new value prevents any compar e during that pwm period. also, using a tim overflow interrupt routine to wr ite a new, smaller pulse width value may cause the compare to be missed. the ti m may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse wi dth, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. tchx period pulse width overflow overflow overflow output compare output compare output compare tchx polarity = 1 (elsxa = 0) polarity = 0 (elsxa = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68hc908qf4 ? rev. 1.0 144 timer interface module (tim) motorola 15.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 stat us and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, t he channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 15.4.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. see table 15-3 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (polarity 1 ? to clear output on compare) or 1:1 (polarity 0 ? to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 15-3 . note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) interrupts mc68hc908qf4 ? rev. 1.0 data sheet motorola timer interface module (tim) 145 or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the buffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 15.9.4 tim channel status and control registers . 15.5 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie =1. chxf and chxie are in the tim channel x status and control register. 15.6 wait mode the wait instruction puts the mcu in low power-consumption standby mode. the tim remains active after the execution of a wait instruction. in wait mode the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68hc908qf4 ? rev. 1.0 146 timer interface module (tim) motorola 15.7 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) contro ls whether status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 16.2.2.5 break flag control register . to allow software to clear status bits during a break interrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 15.8 input/output signals port a shares three of its pins with the tim. two tim channel i/o pins are pta0/tch0 and pta1/tch1 and an alternate clock source is pta2/tclk. 15.8.1 tim clock pin (pta2/tclk) pta2/tclk is an external clock input that can be the clock source for the tim counter instead of the prescaled internal bus clock. select the pta2/tclk input by writing 1s to the three prescaler select bits, ps[2?0]. (see 15.9.1 tim status and control register .) when the pta2/tclk pin is the tim clock input, it is an input regardless of port pin initialization. 15.8.2 tim channel i/o pins (pta0/tch0 and pta1/tch1) each channel i/o pin is programmable inde pendently as an input capture pin or an output compare pin. pta0/tch0 can be configured as a buffered output compare or buffered pwm pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) input/output registers mc68hc908qf4 ? rev. 1.0 data sheet motorola timer interface module (tim) 147 15.9 input/output registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0 and tsc1) tim channel registers (tch0h:tch0l and tch1h:tch1l) 15.9.1 tim status and control register the tim status and control register (tsc) does the following: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. rese t clears the tof bit. writing a 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overfl ow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 15-5. tim status and control register (tsc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68hc908qf4 ? rev. 1.0 148 timer interface module (tim) motorola tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, sto pping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before entering wa it mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after t he tim counter is reset and always reads as a 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneous ly stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the pta2/tclk pin or one of the seven prescaler outputs as the input to the tim counter as table 15-2 shows. reset clears the ps[2:0] bits. table 15-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 pta2/tclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) input/output registers mc68hc908qf4 ? rev. 1.0 data sheet motorola timer interface module (tim) 149 15.9.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. 15.9.3 tim counter modulo registers the read/write tim modulo registers contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note: reset the tim counter before writing to the tim counter modulo registers. address: $0021 tcnth bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0022 tcntl bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 15-6. tim counter registers (tcnth:tcntl) address: $0023 tmodh bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $0024 tmodl bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 15-7. tim counter modulo registers (tmodh:tmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68hc908qf4 ? rev. 1.0 150 timer interface module (tim) motorola 15.9.4 tim channel status and control registers each of the tim channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pi n. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. clear chxf by reading the tim channel x status and control register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing a 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x address: $0025 tsc0 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 address: $0028 tsc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 15-8. tim channel status and control registers (tsc0:tsc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) input/output registers mc68hc908qf4 ? rev. 1.0 data sheet motorola timer interface module (tim) 151 chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 15-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin (see table 15-3 ). reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by wr iting to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). table 15-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 00 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68hc908qf4 ? rev. 1.0 152 timer interface module (tim) motorola elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 15-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note: after initially enabling a tim channel r egister for input capture operation and selecting the edge sensitivity, clear chxf to ignore any erroneous edge detection flags. tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggl e on tim counter overflow. note: when tovx is set, a tim counter overfl ow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is a 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 15-9 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 15-9. chxmax latency output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) input/output registers mc68hc908qf4 ? rev. 1.0 data sheet motorola timer interface module (tim) 153 15.9.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. address: $0026 tch0h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $0027 tch0l bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset address: $0029 tch1h bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset address: $02a tch1l bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 15-10. tim channel registers (tch0h/l:tch1h/l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68hc908qf4 ? rev. 1.0 154 timer interface module (tim) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 155 data sheet ? mc68hc908qf4 section 16. development support 16.1 introduction this section describes the break module, the monitor read-only memory (mon), and the monitor mode entry methods. 16.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features include: accessible input/output (i/o) registers during the break interrupt central processor unit (cpu) generated break interrupts software-generated break interrupts computer operating properly (cop ) disabling during break interrupts 16.2.1 functional description when the internal address bus matches the value written in the break address registers, the break module is sues a breakpoint signal (bkpt ) to the system integration module (sim). the sim then c auses the cpu to load the instruction register with a software interrupt instruction (swi). the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu generated address (the address in the program counter) matches the contents of the break address registers. software writes a 1 to the brka bit in the break status and control register. when a cpu generated address matches the contents of the break address registers, the break interrupt is generated. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the microcontroller unit (mcu) to normal operation. figure 16-2 shows the structure of the break module. figure 16-3 provides a summary of the i/o registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 156 development support motorola figure 16-1. block diagram highlighting brk and mon blocks v cc mode pllen data bs op1 gnd rext xtal1 xtal0 upclk pfd uhf transmitter rst , irq : pins have internal (about 30k ohms) pull up pta[0:5]: high current si nk and source capability pta[0:5]: pins have programmabl e keyboard interrupt and pull up pta0/ad0/tch0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 keyboard interrupt module clock generator (oscillator) system integration module single interrupt module break module power-on reset module 16-bit timer module cop module monitor rom ptb0 ptb ddrb m68hc08 cpu pta ddra ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb7 8-bit adc 128 bytes ram power supply v dd v ss mc68hc908qf4 4096 bytes user flash f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support break module (brk) mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 157 figure 16-2. break module block diagram addr.register name bit 7654321bit 0 $fe00 break status register (bsr) see page 161. read: rrrrrr sbsw r write: note (1) reset: 0 $fe02 break auxiliary register (brkar) see page 160. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe03 break flag control register (bfcr) see page 161. read: bcferrrrrrr write: reset: 0 $fe09 break address high register (brkh) see page 160. read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0a break address low register (brkl) see page 160. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 159. read: brke brka 000000 write: reset:00000000 1. writing a 0 clears sbsw. = unimplemented r = reserved figure 16-3. break i/o register summary address bus[15:8] address bus[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high address bus[15:0] bkpt (to sim) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 158 development support motorola when the internal address bus matches the value written in the break address registers or when software writes a 1 to the brka bit in the break status and control register, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt timing is: when a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. when a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. when software writes a 1 to the brka bit, the break interrupt occurs just before the next instruction is executed. by updating a break address and clearing the brka bit in a break interrupt routine, a break interrupt can be generated continuously. caution: a break address should be placed at the address of the instruction opcode. when software does not change the break address and clears the brka bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 16.2.1.1 flag protection during break interrupts the system integration module (sim) contro ls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 16.2.2.5 break flag control register and the break interrupts subsection for each module. 16.2.1.2 tim during break interrupts a break interrupt stops the timer counter. 16.2.1.3 cop during break interrupts the cop is disabled during a break inte rrupt with monitor mode when bdcop bit is set in break auxiliary register (brkar). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support break module (brk) mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 159 16.2.2 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) break status register (bsr) break flag control register (bfcr) 16.2.2.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match address: $fe0b bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 16-4. break status and control register (brkscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 160 development support motorola 16.2.2.2 break address registers the break address registers (brkh and brkl) contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. 16.2.2.3 break auxiliary register the break auxiliary register (brkar) cont ains a bit that enables software to disable the cop while the mcu is in a stat e of break interrupt with monitor mode. bdcop ? break disable cop bit this read/write bit disables the cop during a break interrupt. reset clears the bdcop bit. 1 = cop disabled during break interrupt 0 = cop enabled during break interrupt. address: $fe09 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 16-5. break address register high (brkh) address: $fe0a bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 figure 16-6. break address register low (brkl) address: $fe02 bit 7654321bit 0 read:0000000 bdcop write: reset:00000000 = unimplemented figure 16-7. break auxiliary register (brkar) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support break module (brk) mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 161 16.2.2.4 break status register the break status register (bsr) contains a flag to indicate that a break caused an exit from wait mode. this register is only used in emulation mode. sbsw ? sim break stop/wait sbsw can be read within the break state sw i routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt 16.2.2.5 break flag control register the break control register (bfcr) contai ns a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a 0 clears sbsw. figure 16-8. break status register (bsr) address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 16-9. break flag control register (bfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 162 development support motorola 16.2.3 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. if enabled, the break module will re main enabled in wait and stop modes. however, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. 16.3 monitor module (mon) this subsection describes the monitor module (mon) and the monitor mode entry methods. the monitor allows debugging and programming of the microcontroller unit (mcu) through a single-wire interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. features include: normal user-mode pin functionality on most pins one pin dedicated to serial communication between mcu and host computer standard non-return-to-zero (nrz) communication with host computer execution of code in random-access memory (ram) or flash flash memory security feature (1) flash memory programming interface use of external 9.8304 mhz oscillat or to generate internal frequency of 2.4576 mhz simple internal oscillator mode of oper ation (no external clock or high voltage) monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage is applied to irq 16.3.1 functional description figure 16-10 shows a simplified diagram of monitor mode entry. the monitor module receives and execut es commands from a host computer. figure 16-11 , figure 16-12 , and figure 16-13 show example circuits used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support monitor module (mon) mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 163 figure 16-10. simplified monitor mode entry flowchart monitor mode entry por reset pta0 = 1, pta1 = 1, and pta4 = 0? irq = v tst ? yes no yes no forced monitor mode normal user mode normal monitor mode invalid user mode no no host sends 8 security bytes is reset por? yes yes yes no are all security bytes correct? no yes enable flash disable flash execute monitor code does reset occur? conditions from table 16-1 debugging and flash programming (if flash is enabled) pta0 = 1, reset vector blank? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 164 development support motorola simple monitor commands can access any memory address. in monitor mode, the mcu can execute code downloaded into ram by a host computer while most mcu pins retain normal operating mode functi ons. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and th e host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. the monitor code has been updated from pr evious versions of the monitor code to allow enabling the internal oscillator to g enerate the internal clock. this addition, which is enabled when irq is held low out of reset, is intended to support serial communication/programming at 4800 baud in monitor mode by using the internal oscillator, and the internal oscillator us er trim value osctrim (flash location $ffc0, if programmed) to generate the desired internal frequency (1.0 mhz). since this feature is enabled only when irq is held low out of reset, it cannot be used when the reset vector is programm ed (i.e., the value is not $ffff) because entry into monitor mode in this case requires v tst on irq . the irq pin must remain low during this monitor sessi on in order to maintain communication. table 16-1 shows the pin conditions for entering monitor mode. as specified in the table, monitor mode may be entered after a power-on reset (por) and will allow communication at 9600 baud provided one of the following sets of conditions is met: if $fffe and $ffff do not contain $ff (programmed state): ? the external clock is 9.8304 mhz ?irq = v tst if $fffe and $ffff contain $ff (erased state): ? the external clock is 9.8304 mhz ?irq = v dd (this can be implemented through the internal irq pullup) if $fffe and $ffff contain $ff (erased state): ?irq = v ss (internal oscillator is selected, no external clock required) the rising edge of the internal rst signal latches the monitor mode. once monitor mode is latched, the values on pta1 and pta4 pins can be changed. once out of reset, the mcu waits for the host to send eight security bytes (see 16.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecutive logic 0s) to the host, indicati ng that it is ready to receive a command. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support monitor module (mon) mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 165 figure 16-11. monitor mode circuit (external clock, with high voltage) figure 16-12. monitor mode circuit (external clock, no high voltage) 9.8304 mhz clock + 10 k ? * v dd 10 k ? * rst (pta3) irq (pta2) pta0 osc1 (pta5) 8 7 db9 2 3 5 16 15 2 6 10 9 v dd max232 v+ v? 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? pta1 pta4 v ss 0.1 f v dd 1 k ? 9.1 v c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + 1 f v dd + 1 f v tst * value not critical v dd v dd 10 k ? * rst (pta3) irq (pta2) pta0 osc1 (pta5) 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? n.c. pta1 n.c. pta4 v ss 0.1 f v dd 9.8304 mhz clock c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd 10 k ? * * value not critical n.c. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 166 development support motorola figure 16-13. monitor mode circuit (internal clock, no high voltage) 16.3.1.1 normal monitor mode rst and osc1 functions will be active on the pta3 and pta5 pins respectively as long as v tst is applied to the irq pin. if the irq pin is lowered (no longer v tst ) then the chip will still be operating in m onitor mode, but the pin functions will be determined by the settings in the configuration registers (see section 5. configuration register (config) ) when v tst was lowered. with v tst lowered, the bih and bil instructions will read the irq pin state only if irqen is set in the config2 register. if monitor mode was entered with v tst on irq , then the cop is disabled as long as v tst is applied to irq . rst (pta3) irq (pta2) pta0 10 k ? * osc1 (pta5) n.c. 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 c1+ c1? v+ v? 5 4 1 f c2+ c2? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? n.c. pta1 n.c. pta4 v ss 0.1 f v dd + 3 1 1 f + + + 1 f v dd * value not critical n.c. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 167 development support monitor module (mon) table 16-1. monitor mode signal requirements and options mode irq (pta2) rst (pta3) reset vector serial communication mode selection cop communication speed comments pta0 pta1 pta4 external clock bus frequency baud rate normal monitor v tst v dd x 1 1 0 disabled 9.8304 mhz 2.4576 mhz 9600 provide external clock at osc1. forced monitor v dd x $ffff (blank) 1 x x disabled 9.8304 mhz 2.4576 mhz 9600 provide external clock at osc1. v ss x $ffff (blank) 1 x x disabled x 1.0 mhz (trimmed) 4800 internal clock is active. user x x not $ffff xxxenabledxxx mon08 function [pin no.] v tst [6] rst [4] ? com [8] mod0 [12] mod1 [10] ? osc1 [13] ?? 1. pta0 must have a pullup resistor to v dd in monitor mode. 2. communication speed in the table is an example to obtain a baud rate of 9600. baud rate using external oscillator is bus fre quency / 256 and baud rate using internal oscillator is bus frequency / 206. 3. external clock is a 9.8304 mhz oscillator on osc1. 4. x = don?t care 5. mon08 pin refers to p&e microcomputer s ystems? mon08-cyclone 2 by 8-pin connector. nc 1 2 gnd nc 3 4 rst nc 5 6 irq nc 7 8 pta0 nc 9 10 pta4 nc 11 12 pta1 osc1 13 14 nc v dd 15 16 nc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 168 development support motorola 16.3.1.2 forced monitor mode if entering monitor mode without high voltage on irq , then startup port pin requirements and conditions, (pta1/pta4) ar e not in effect. this is to reduce circuit requirements when performing in-circuit programming. note: if the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (por). once the reset vector has been programmed, the traditional method of applying a voltage, v tst , to irq must be used to enter monitor mode. if monitor mode was entered as a result of the reset vector being blank, the cop is always disabled regardless of the state of irq . if the voltage applied to the irq is less than v tst , the mcu will come out of reset in user mode. internal circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($ff). when the mcu comes out of reset, it is forced into monitor mode without requiring high voltage on the irq pin. once out of reset, the monitor code is initially executing with the internal clock at its default frequency. if irq is held high, all pins will default to regular input port functions except for pta0 and pta5 which will operate as a serial communication port and osc1 input respectively (refer to figure 16-12 ). that will allow the clock to be driven from an external source through osc1 pin. if irq is held low, all pins will default to regular input port function except for pta0 which will operate as serial communication port. refer to figure 16-13 . regardless of the state of the irq pin, it will not function as a port input pin in monitor mode. bit 2 of the port a data register will always read 0. the bih and bil instructions will behave as if the irq pin is enabled, regardles s of the settings in the configuration register. see section 5. configuration register (config) . the cop module is disabled in forced monitor mode. any reset other than a power-on reset (por) will automatically force the mcu to come back to the forced monitor mode. 16.3.1.3 monitor vectors in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. note: exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (por). pulling rst (when rst pin available) low will not exit monitor mode in this situation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support monitor module (mon) mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 169 table 16-2 summarizes the differences between user mode and monitor mode regarding vectors. 16.3.1.4 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. transmit and receive baud rates must be identical. figure 16-14. monitor data format 16.3.1.5 break signal a start bit (logic 0) followed by nine logi c 0 bits is a break signal. when the monitor receives a break signal, it drives the pt a0 pin high for the duration of two bits and then echoes back the break signal. figure 16-15. break transaction 16.3.1.6 baud rate the monitor communication baud rate is controlled by the frequency of the external or internal oscillator and the state of the appropriate pins as shown in table 16-1 . table 16-1 also lists the bus frequencies to achieve standard baud rates. the effective baud rate is the bus frequenc y divided by 256 when us ing an external oscillator. when using the inte rnal oscillator in forced monitor mode, the effective baud rate is the bus frequency divided by 206. table 16-2. mode difference modes functions reset vector high reset vector low break vector high break vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd $fffc $fffd monitor $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 7 bit 0 bit 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop bit delay before zero echo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 170 development support motorola 16.3.1.7 commands the monitor rom firmware uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each re ceived byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note: wait one bit time after each ec ho before sending the next byte. figure 16-16. read transaction figure 16-17. write transaction a brief description of each moni tor mode command is given in table 16-3 through table 16-8 . read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, approximately 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, approximately 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, approximately 2 bit times f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support monitor module (mon) mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 171 table 16-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 16-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence table 16-5. iread (indexed read) command description read next 2 bytes in memory from last ad dress accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data iread iread echo data return data from host f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 172 development support motorola a sequence of iread or iwrite comman ds can access a block of memory sequentially over the full 64-kbyte memory map. table 16-6. iwrite (indexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 16-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 16-8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence iwrite iwrite echo from host data data readsp readsp echo from host sp return sp high low run run echo from host f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support monitor module (mon) mc68hc908qf4 ? rev. 1.0 data sheet motorola development support 173 the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instructions. before sending the run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 16-18. stack pointer at monitor mode entry 16.3.2 security a security feature discourages unauthori zed reading of flash locations while in monitor mode. the host can bypass the se curity feature at monitor mode entry by sending eight security bytes that matc h the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note: do not leave locations $fff6?$fffd blank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin pta0 . if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from fl ash. security remains bypassed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. see figure 16-19 . upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character until after the host sends the eight security bytes. condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908qf4 ? rev. 1.0 174 development support motorola figure 16-19. monitor mode entry timing to determine whether the security code entered is correct, check to see if bit 6 of ram address $80 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the devic e should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the security sequence, the flash module can also be mass erased by executing an erase routine that was downloaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 cgmxclk cycles 1 3 1 1 2 1 break notes: 2 = data return delay, approximately 2 bit times 3 = wait 1 bit time before sending next byte 3 from host from mcu 1 = echo delay, approximately 2 bit times 4 4 = wait until clock is stable and monitor runs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola electrical specifications 175 data sheet ? mc68hc908qf4 section 17. electrical specifications 17.1 introduction this section contains electric al and timing specifications. 17.2 absolute maximum ratings maximum ratings are the extreme limits to which the microcontroller unit (mcu) can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to 17.5 dc electrical characteristics for guaranteed operating conditions. note: this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields; however , it is advised that normal precautions be taken to avoid application of any volta ge higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd .) characteristic (1) 1. voltages references to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v mode entry voltage, irq pin v tst v ss ?0.3 to +9.1 v maximum current per pin excluding pta0?pta5, v dd , and v ss i15ma maximum current for pins pta0?pta5 i pta0? i pta5 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908qf4 ? rev. 1.0 176 electrical specifications motorola 17.3 functional o perating range 17.4 thermal characteristics characteristic symbol value unit temp code operating temperature range (t l to t h ) t a ?40 to 85 0 to 70 c c ? operating voltage range (1) (v ddmin to v ddmax ) ?40 to 85c 0 to 70c 1. v dd must be above v tripr upon power on. v dd 2.4 to 3.6 2.2 to 3.6 vc ? characteristic symbol value unit thermal resistance 32-pin tqfp ja 72 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273c) w constant (2) 2. k constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273c) + p d 2 x ja w/c average junction temperature t j t a + (p d x ja ) c maximum junction temperature t jm 150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications dc electrical characteristics mc68hc908qf4 ? rev. 1.0 data sheet motorola electrical specifications 177 17.5 dc electrica l characteristics characteristic (1) symbol min typ (2) max unit output high voltage (for v dd > 2.7 v) i load = ?4 ma i load = ?10 ma, pta0, pta1, pta3?pta5 only v oh v dd ?0.8 v dd ?0.8 ? ? ? ? v output high voltage (for v ddmin < v dd < v ddmax ) i load = ?2 ma i load = ?5 ma, pta0, pta1, pta3?pta5 only v oh v dd ?0.8 v dd ?0.8 ? ? ? ? v output low voltage (for v dd > 2.7 v) i load = 4 ma i load = 10 ma, pta0, pta1, pta3?pta5 only v ol ? ? ? ? 0.8 0.8 v output low voltage (for v ddmin < v dd < v ddmax ) i load = 2 ma i load = 5 ma, pta0, pta1, pta3?pta5 only v ol ? ? ? ? 0.8 0.8 v maximum combined i oh (all i/o pins) i oht ??50ma maximum combined i ol (all i/o pins) i olt ??50ma input high voltage pta0?pta5, ptb0?ptb7 v ih 0.7 x v dd ? v dd v input low voltage pta0?pta5, ptb0?ptb7 v il v ss ? 0.3 x v dd v input hysteresis v hys 0.06 x v dd ??v dc injection current, all ports i inj ?2 ? +2 ma total dc current injection (sum of all i/o) i injtot ?25 ? +25 ma digital i/o ports hi-z leakage current typical at 25c i il ?1 ? ? 0.1 +1 ? a digital input only ports leakage current (pa2/irq /kbi2 ) i in ?1 ? +1 a capacitance ports (as input) ports (as output) c in c out ? ? ? ? 12 8 pf por rearm voltage (3) v por 0?100mv por rise time ramp rate (4) r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 ?9.1v pullup resistors (5) pta0?pta5, ptb0?ptb7 r pu 16 26 36 k ? ? continued on next page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908qf4 ? rev. 1.0 178 electrical specifications motorola 17.6 control timing figure 17-1. rst and irq timing low-voltage inhibit reset, trip falling voltage (lvr) v tripf 2.00 2.12 2.24 v low-voltage inhibit reset, trip rising voltage (lvr) v tripr 2.04 2.18 2.30 v low-voltage inhibit reset/recover hysteresis v hys ?60?mv low-voltage detect, trip falling voltage (lvd) v dtripf 2.20 2.32 2.44 v low-voltage detect, trip rising voltage (lvd) v dtripr 2.21 2.33 2.45 v low-voltage detect reset/recover hysteresis v dhys ?10?mv 1. v dd = v ddmin to v ddmax , v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurements at v dd = 3.0 v, 25c only. 3. maximum is highest vo ltage that por is guaranteed. 4. if minimum v dd is not reached before the internal por reset is rele ased, the lvi will hold the part in reset until minimum v dd is reached. 5. r pu is measured at v dd = 3.0 v. characteristic (1) symbol min typ (2) max unit characteristic (1) symbol min max unit internal operating frequency f op (f bus ) ?2mhz internal clock period (1/f op )t cyc 500 ? ns rst input pulse width low t rl 400 ? ns irq interrupt pulse width low (edge-triggered) t ilih 400 ? ns irq interrupt pulse period t ilil note (2) ? t cyc 1. v dd > 2.2 v, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd unless otherwise noted. 2. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . rst irq t rl t ilih t ilil f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications typical 3.0-v output drive characteristics mc68hc908qf4 ? rev. 1.0 data sheet motorola electrical specifications 179 17.7 typical 3.0-v output drive characteristics figure 17-2. typical 3-volt output high voltage versus output high current (25c) figure 17-3. typical 3-volt output low voltage versus output low current (25c) 0.0 0.5 1.0 1.5 -20 -15 -10 -5 0 ioh (ma) vdd-voh (v) 3v pta 3v ptb 0.0 0.5 1.0 1.5 0 5 10 15 20 iol (ma) vol (v) 3v pta 3v ptb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908qf4 ? rev. 1.0 180 electrical specifications motorola 17.8 oscillator characteristics figure 17-4. typical rc oscillator frequency versus r ext (25c) characteristic symbol min typ max unit internal oscillator frequency (1) f intclk ?4.0?mhz crystal frequency, xtalclk (1) f oscxclk 30 32.768 100 khz external rc oscillator frequency, rcclk (1) f rcclk 2?8mhz external clock reference frequency (1), (2) f oscxclk dc ? 8 mhz crystal load capacitance (3) c l ?12.5? pf crystal fixed capacitance (3) c 1 ? 2 x c l ?? crystal tuning capacitance (3) c 2 ? 2 x c l ?? feedback bias resistor r b ?10?m ? series resistor r s 270 330 360 k ? rc oscillator external resistor r ext see figure 17-4 ? 1. bus frequency, f op , is oscillator frequency divided by 4. 2. no more than 10% duty cycle deviation from 50%. 3. consult crystal vendor data sheet. r ext osc1 v dd mcu 0 2 4 6 8 10 12 0 102030405060 r ext (k ? ) f rcclk (mhz) 3v 2.3v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications supply current characteristics mc68hc908qf4 ? rev. 1.0 data sheet motorola electrical specifications 181 17.9 supply current characteristics figure 17-5. typical run current versus v dd (25c) (f bus = 1 mhz for internal oscillator, f bus = 8 khz for crystal oscillator) characteristic voltage bus freq. (mhz) symbol typ max unit run mode v dd supply current (1) 3.0 2.2 1 1 ri dd 1.5 1.0 2.5 1.5 ma wait mode v dd supply current (2) 3.0 2.2 1 1 wi dd 1.2 1.0 2.0 1.0 ma stop mode v dd supply current (3) 25 c 0 to 70c ?40 to 85c 25 c with auto wake-up enabled incremental current with lvi enabled at 25 c 3.0 si dd 0.006 0.08 0.12 5.70 110 ? ? 2.0 ? ? a 25 c 0 to 70c ?40 to 85c 25 c with auto wake-up enabled incremental current with lvi enabled at 25 c 2.2 0.005 0.08 0.12 1.30 100 ? ? 1.0 ? ? a 1. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports configured as inpu ts. measured with all modules except adc enabled. 2. wait (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports configured as inpu ts. measured with all modules except adc enabled. 3. stop i dd measured with all ports driven 0.2 v or less from rail. no dc loads. on the 8-pin versions, port b is configured as inputs with pullups enabled. 0 0.5 1 1.5 2 2.5 22.533.54 v dd (v) run i dd (ma) int osc w/ adc int osc w/o adc 32k crystal w/ adc 32k crystal w/o adc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908qf4 ? rev. 1.0 182 electrical specifications motorola figure 17-6. typical wait current versus v dd (25c) f bus = 1 mhz for internal oscillator, f bus = 8 khz for crystal oscillator) figure 17-7. typical stop current versus v dd (25c) 0 0.2 0.4 0.6 0.8 1 2 2.5 3 3.5 4 v dd (v) wait i dd (ma) int osc w/ adc int osc w/o adc 32k crystal w/ adc 32k crystal w/o adc 0 2 4 6 8 10 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 v dd (v) stop i dd (na) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications analog-to-digital (adc) c onverter characteristics mc68hc908qf4 ? rev. 1.0 data sheet motorola electrical specifications 183 17.10 analog-to-digital (a dc) converter characteristics 17.10.1 adc electrical operating conditions the adc accuracy characteristics below are guaranteed over two operating conditions as stated here. 17.10.2 adc performance characteristics characteristic symbol min max unit condition a atd supply v dd 2.7 3.6 v adc internal clock f adic 0.008 1 mhz ambient temperature t a t l t h c condition b atd supply v dd 2.3 2.7 v adc internal clock f adic 863khz ambient temperature t a 0 t h c characteristic symbol min max unit comments input voltages v adin v ss v dd v? resolution (1 lsb) condition a condition b res 10.5 8.99 14.1 10.5 mv ? absolute accuracy condition a (total unadjusted error) condition b e tue ? ? 1.5 2.0 lsb includes quantization conversion range v ain v ss v dd v? power-up time t adpu 16 ? t adic cycles t adic = 1/f adic conversion time t adc 16 17 t adic cycles t adic = 1/f adic sample time (1) t ads 5? t adic cycles t adic = 1/f adic zero input reading (2) z adi 00 01 hex v in = v ss full-scale reading (3) f adi fe ff hex v in = v dd input capacitance c adi ? 8 pf not tested input leakage (3) i il ? 1 a? adc supply current (v dd = 3 v) i adad typical = 0.45 ma enabled 1. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. 2. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. 3. the external system error caused by input leakage current is approximately equal to the product of r source and input current. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908qf4 ? rev. 1.0 184 electrical specifications motorola 17.11 timer interface mo dule characteristics figure 17-8. timer input timing characteristic symbol min max unit timer input capture pulse width t th, t tl 2? t cyc timer input capture period t tltl note (1) ? t cyc timer input clock pulse width t tcl , t tch t cyc + 5 ?ns 1. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . input capture rising edge input capture falling edge input capture both edges t th t tl t tltl t tltl t tltl t tl t th tclk t tcl t tch f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications memory characteristics mc68hc908qf4 ? rev. 1.0 data sheet motorola electrical specifications 185 17.12 memory characteristics characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash program bus clock frequency ? 1 ? ? mhz flash pgm/erase supply voltage (v dd )v pgm/erase 2.7 ? 3.6 v flash read bus clock frequency f read (1) 0?2mhz flash page erase time <1 k cycles >1 k cycles t erase 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase 4??ms flash pgm/erase to hven setup time t nvs 10 ? ? s flash high-voltage hold time t nvh 5?? s flash high-voltage hold time (mass erase) t nvhl 100 ? ? s flash program setup time t pgs 5?? s flash program time t prog 30 ? 40 s flash return to read time t rcv (2) 1??ms flash cumulative program hv period t hv (3) ?? 4ms flash endurance (4) ? 10 k 100 k ? cycles flash data retention time (5) ? 15 100 ? years 1. f read is defined as the frequency range for which the flash memory can be read. 2. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to 0. 3. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 32) t hv maximum. 4. typical endurance was evaluated for this product family. for additional information on how motorola defines typical endurance , please refer to engineering bulletin eb619. 5. typical data retention values are based on intrinsic capability of the technology measured at high temp erature and de-rated to 25c using the arrhenius equation. for additional information on how motorola defines typical data retention , please refer to engineering bulletin eb618. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908qf4 ? rev. 1.0 186 electrical specifications motorola 17.13 uhf tran smitter module this subsection provides elec trical specifications and ti ming definitions for the uhf transmitter module. 17.13.1 uhf module electrical characteristics unless otherwise specified: v cc = 3 v r ext = 12 k ? operating temperature range (t a ) = ?40c to 85c rf output frequency: f carrier = 433.92 mhz reference frequency: f reference =13.56 mhz ook modulation selected output load is 50 ? resistor (see figure 17-12 ) values refer to the circuit shown in the recommended application schematic (see figure 12-5. application schematic in ook modulation, 315-mhz and 434-mhz frequency bands ). typical values reflect average measurement at v cc = 3 v, t a = 25 c. parameter test conditions and comments min typ max unit general parameters supply current in standby mode t a 25c ?0.1 5 na t a = 60c ? 7 30 na t a = 85c ? 40 100 na supply current in transmission mode 315 and 434 mhz bands, continuous wave, t a 85c ? 11.6 13.5 ma 315 and 434 mhz bands, data = 0, ?40c t a 85c ?4.46.0ma 868 mhz band, data = 0, ?40c t a 85c ?4.66.2ma 868 mhz band, continuous wave, ?40c t a 85c ? 11.8 15.1 ma ? continued on next page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications uhf transmitter module mc68hc908qf4 ? rev. 1.0 data sheet motorola electrical specifications 187 supply voltage ? 3 3.6 v shutdown voltage threshold t a = ?40c ?2.042.11 v t a = ?20c ?1.992.06 v t a = 25c ?1.861.95 v t a = 60c ?1.761.84 v t a = 85c ?1.681.78 v t a = 125c ?1.561.67 v rf parameters (assuming a 50 ? matching network connecte d to the d.u.t. output) r ext value 12 ? 21 k ? output power 315 and 434 mhz bands, with 50 ? matching network ?5?dbm 868 mhz band, with 50 ? matching network ?1?dbm 315 and 434 mhz bands, ?40c t a 125c ?3 0 3 dbm 868 mhz band, ?40c t a 125c ?7 ?3 0 dbm current and output power variation vs r ext value 314 and 434 mhz bands, with 50 ? matching network ? ?0.35 ? db/k ? ma/k ? harmonic 2 level 315 and 434 mhz bands, with 50 ? matching network ??34?dbc 868 mhz band, with 50 ? matching network ??49?dbc 315 and 434 mhz bands ? ?23 ?17 dbc 868 mhz band ? ?38 ?27 dbc harmonic 3 level 315 and 434mhz bands, with 50 ? matching network ??32?dbc 868 mhz band, with 50 ? matching network ??57?dbc 315 and 434 mhz bands ? ?21 ?15 dbc 868 mhz band ? ?48 ?39 dbc spurious level @ f carrier f dataclk 315 and 434 mhz bands ? ?36 ?24 dbc 868 mhz band ?29 ?17 dbc spurious level @ f carrier f reference 315 mhz band ? ?37 ?30 dbc 434 mhz band ? ?44 ?34 dbc 868 mhz band ? ?37 ?27 dbc ? continued on next page parameter test conditions and comments min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908qf4 ? rev. 1.0 188 electrical specifications motorola spurious level @ f carrier /2 315 mhz bands ? ?62 ?53 dbc 434 mhz bands ? ?80 ?60 dbc 868 mhz band ? ?45 ?39 dbc rf spectrum 434 mhz bands see figure 17-9 , figure 17-10 , and figure 17-11 ? phase noise 315 and 434 mhz bands, 175 khz from f carrier ? ?75 ?68 dbc/hz 868 mhz band, 175 khz from f carrier ? ?73 ?66 dbc/hz pll lock-in time, t pll_lock_in f carrier within 30 khz from the final value, crystal series resistor = 150 ? ? 400 1600 s xtal1 input capacitance ? 1 2 pf crystal resistance ook modulation ? 20 200 ? fsk modulation ? 20 50 ook modulation depth 75 90 ? dbc data rate ??10kbit/s microcontroller interfaces input low voltage pins band, mode, enable, and data 0? 0.3 x v cc v input high voltage 0.7 x v cc ? v cc v input hysteresis voltage ? ? 150 mv input current pins band, mode, data @ high level ? ? 100 na enable pulldown resistor ? 180 ? k ? dataclk output low voltage c load = 2 pf 0? 0.25 x v cc v dataclk output high voltage 0.75 x v cc ? v cc v dataclk rising time c load = 2 pf, measured from 20% to 80% of the voltage swing ? 250 500 ns dataclk falling time ? 150 400 ns dataclk settling time, t dataclk_settling 45 < duty cycle f dataclk < 55% ? 800 1800 s parameter test conditions and comments min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications uhf transmitter module mc68hc908qf4 ? rev. 1.0 data sheet motorola electrical specifications 189 figure 17-9. rf spectrum at 434-mhz frequency band displayed with a 5-mhz span figure 17-10. rf spectrum at 434-mhz frequency band displayed with a 50-mhz span resolution bandwidth: 100 khz resolution bandwidth: 30 khz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908qf4 ? rev. 1.0 190 electrical specifications motorola figure 17-11. rf spectrum at 434-mhz frequency band displayed with a 1.5-ghz span 17.13.2 uhf module output power measurement the rf output levels given in the 17.13.1 uhf module electrical characteristics are measured whith a 50- ? load directly connected to the pin rfout as shown in figure figure 17-12 . this wideband coupling method gives results independant of the application. figure 17-12. output power measurement configurations rfout rf output 50 ? 100 pf impeder: tdk mmz1608y102cta00 v cc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications uhf transmitter module mc68hc908qf4 ? rev. 1.0 data sheet motorola electrical specifications 191 the configuration shown in figure 17-13 (a) provides a better efficiency in terms of output power and harmonics rejection. schematic in figure 17-13 (b) gives the equivalent circuit of the pin rfout and impeder as well as the matching network components for 434-mhz frequency band. note: note that the impeder is moved to the load side to decrease its influence (similar to dc bias through the antenna). figure 17-14 gives the output power versus the r ext resistor value, in both cases with 50- ? load and with matching network. figure 17-13. ouput characteristic and matching network for 434-mhz frequency band rfout rf output 50 ? impeder: tdk mmz1608y102cta00 v cc matching network c 0 r 0 r i r l l 1 1.5 pf 250 ? 3 k ? 50 ? matching 330 pf c 3 39 nh rfout pin load impeder (a) (b) network f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908qf4 ? rev. 1.0 192 electrical specifications motorola figure 17-14. output power at 434-mhz frequency band versus r ext value rfout level (dbm) 8 6 4 2 0 ?2 ?4 ?6 6 9 12 15 18 21 24 r ext (k ? ) output power on 50 ? load (dbm) output power when matched (dbm) ?0.35 db/k ? # ?0.35 ma/k ? r ext specified range output power measurement in typical conditions (434 mhz ? v cc = 3 v ?25 c) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908qf4 ? rev. 1.0 data sheet motorola ordering information and mechanical specifications 193 data sheet ? mc68hc908qf4 section 18. ordering informatio n and mechanical specifications 18.1 introduction this section provides ordering information and mechanical specifications for the 32-pin low-profile quad flat pack (lqfp). the package outline given here reflects the latest package drawing at the time of publication. to make sure that you have the latest package s pecification, contact your local motorola sales office. 18.2 mc order numbers figure 18-1. device numbering system table 18-1. available mc order numbers mc order number operating temperature range package mc908qf4cfj ?40c to +85c 32-pin lqfp mc908qf4fj 0c to +70c 32-pin lqfp temperature and package designators: c = ?40c to +85c fj = low-profile quad flat pack (lqfp) m c 9 0 8 q f 4 c f j family package designator temperature range blank = 0 to 70c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information and mechanical specifications data sheet mc68hc908qf4 ? rev. 1.0 194 ordering information and mechanical specifications motorola 18.3 32-pin plastic lo w-profile quad flat pack (case no. 873a) 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 ?t? ?z? ?u? t?u 0.20 (0.008) z ac t?u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t?u m 0.20 (0.008) z ac f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc6 8 hc908q f 4 rev. 1.0 6/2004 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any produc t or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. ?typical? parameters that may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intend ed for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola inc. 2004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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